CY241V08A-02 Cypress Semiconductor, CY241V08A-02 Datasheet

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CY241V08A-02

Manufacturer Part Number
CY241V08A-02
Description
MPEG Clock Generator
Manufacturer
Cypress Semiconductor
Datasheet
Cypress Semiconductor Corporation
Document #: 38-07674 Rev. *A
Features
Frequency Table
CY241V08A-02
• Robust Oscillator
• Low-jitter, high-accuracy outputs
• VCXO with analog adjust
• 3.3V operation
Pin Configuration
Part Number
Block Diagram
VCXO
VDD
VSS
XIN
CY241V08A-02
8-pin SOIC
1
2
3
4
27 XIN
Outputs
VCXO
XOUT
1
8
7
6
5
XOUT
NC or VSS
NC or VDD
27 MHz
27-MHz pullable crystal input
per Cypress specification
OSC
Input Frequency Range
VDD
3901 North First Street
PRELIMINARY
VSS
MPEG Clock Generator with VCXO
One copy of 27 MHz
Output Frequencies
Benefits
• Highest-performance oscillator tailored for multimedia
• Meets critical timing requirements in complex system
• Application compatibility for a wide variety of designs
applications
designs
San Jose
VCXO Control
linear
Curve
,
XBUF/27MHz
CA 95134
Low Jitter Non-PLL
Revised March 21, 2005
CY241V08A-02
Other Features
www.DataSheet4U.com
408-943-2600

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CY241V08A-02 Summary of contents

Page 1

... Application compatibility for a wide variety of designs Output Frequencies One copy of 27 MHz VDD VSS • 3901 North First Street • San Jose www.DataSheet4U.com CY241V08A-02 VCXO Control Curve Other Features linear Low Jitter Non-PLL XBUF/27MHz , CA 95134 • 408-943-2600 Revised March 21, 2005 ...

Page 2

... Pin Number XIN 1 Reference crystal input. VDD 2 Voltage supply. VCXO 3 Input analog control for VCXO. VSS 4 Ground. XBUF/27 MHz 5 27-MHz buffered crystal output Connect or VDD Connect or VSS XOUT 8 Reference crystal output. Document #: 38-07674 Rev. *A PRELIMINARY Description CY241V08A-02 www.DataSheet4U.com Page ...

Page 3

... Output Clock Edge Rate, Measured from 20 pF. See Figure 2. DD LOAD Output Clock Edge Rate, Measured from 80 pF. See Figure 2. DD LOAD 27-MHz Clock Jitter CY241V08A-02 www.DataSheet4U.com Min. Typ. Max. Unit – 27 – MHz – 14 – – – ...

Page 4

... Document #: 38-07674 Rev. *A PRELIMINARY 0.1 µF DUT GND Figure 1. Duty Cycle Definition Figure (0 /t3 (0 Package Type Operating Range Commercial CY241V08A-02 www.DataSheet4U.com Outputs C LOAD /t4 DD Operating Voltage Features 3 ...

Page 5

... S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. SEATING PLANE 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.004[0.102] 0°~8° 0.016[0.406] 0.0098[0.249] 0.035[0.889] CY241V08A-02 www.DataSheet4U.com MAX. PART # 0.010[0.254] X 45° 0.016[0.406] 0.0075[0.190] 0.0098[0.249] 51-85066-*C Page ...

Page 6

... Document History Page Document Title: CY241V08A-02 MPEG Clock Generator with VCXO Document Number: 38-07674 REV. ECN NO. Issue Date ** 222320 See ECN *A 338335 See ECN Document #: 38-07674 Rev. *A PRELIMINARY Orig. of Change Description of Change RGL New Data Sheet RGL Added Lead-free CY241V08A-02 www.DataSheet4U.com ...

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