CY28158PVCT Cypress Semiconductor, CY28158PVCT Datasheet

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CY28158PVCT

Manufacturer Part Number
CY28158PVCT
Description
Spread Spectrum Timing Solution for Serverworks Chipset
Manufacturer
Cypress Semiconductor
Datasheet
Cypress Semiconductor Corporation
Document #: 38-07039 Rev. *B
Features
• Maximized EMI suppression using Cypress’s spread
• Based on Industry Standard CK133 Pinout with all out-
• 0.5% downspread outputs deliver up to 10dB lower EMI
• 6 skew-controlled copies of CPU output
• 6 copies of PCI output (synchronous w/CPU output)
• 2 copies of 66 MHz fixed frequency 3.3V clock
• 3 copies of 16.67 MHz IOAPIC clock, synchronous to
• 1 copy of 48 MHz USB output
• 2 copies of 14.31818 MHz reference clock
• Programmable to 133 or 100 MHz operation
• Power management control pins for clock stop and
• Available in 56-pin SSOP
Block Diagram
spectrum technology
puts compliant to CK98 specifications
CPU clock
shut down
CPU_STOP#
SEL133/100#
PCI_STOP#
PWRDWN#
SPREAD#
X1
X2
SEL0
SEL1
Spread Spectrum Timing Solution for Serverworks Chipset
PLL2
Power
Down
XTAL
PLL 1
Logic
OSC
Tristate
Logic
÷2
÷2/÷1.5
÷2
Clock
STOP
Logic
STOP
Clock
STOP
Clock
Logic
Logic
3901 North First Street
1
2
6
1
3
5
2
REF0:1
CPU0:5
3V66_0:1
PCI_F
PCI1:5
IOAPIC0:2
48MHz
Key Specifications
Supply Voltages:...................................... V
CPU Output Jitter: ....................................................<150 ps
CPU Output Skew: ....................................................<175 ps
CPU to 3V66 Output Offset:
CPU to IOAPIC Output Offset
CPU to PCI Output Offset................. 0 to 4.0 ns (CPU leads)
Table 1. Pin Selectable Frequency.
................................................................ V
SEL133/100#
SEL133/100#
Pin Configuration
GND_3V66
GND_3V66
GND_3V66
VDD_3V66
VDD_3V66
VDD_3V66
GND_REF
VDD_REF
GND_PCI
GND_PCI
GND_PCI
GND_PCI
VDD_PCI
VDD_PCI
VDD_PCI
3V66_0
3V66_1
1
0
PCI_F
REF0
REF1
San Jose
PCI1
PCI2
PCI3
PCI4
PCI5
X1
X2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CPU0:5 (MHz)
CA 95134
133
100
0.0 to1.5 ns (CPU leads)
1.5 to 4.0 ns (CPU leads)
32
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
31
30
29
Revised June 25, 2004
DD33
DD25
VDD_IOAPIC
IOAPIC2
IOAPIC1
IOAPIC0
GND_IOAPIC
VDD_CPU
CPU5
CPU4
GND_CPU
VDD_CPU
CPU3
CPU2
GND_CPU
VDD_CPU
CPU1
CPU0
GND_CPU
VDDA
GNDA
PCI_STOP#
CPU_STOP#
PWR_DWN#
SPREAD#
SEL1
SEL0
VDD_48MHZ
48MHZ
GND_48MHZ
CY28158
408-943-2600
= 3.3V ± 5%
= 2.5V ± 5%
33.3
33.3
PCI

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CY28158PVCT Summary of contents

Page 1

... PWRDWN# PCI_STOP# Power Down Logic Tristate Logic PLL2 Cypress Semiconductor Corporation Document #: 38-07039 Rev. *B Key Specifications Supply Voltages:...................................... V ................................................................ V CPU Output Jitter: ....................................................<150 ps CPU Output Skew: ....................................................<175 ps CPU to 3V66 Output Offset: CPU to IOAPIC Output Offset CPU to PCI Output Offset................. 0 to 4.0 ns (CPU leads) Table 1 ...

Page 2

Pin Definitions Name Pins [ [ CPU [0–5] 41, 42, 45, 46, 49, 50 PCI [1–5] 11, 12, 14, 15, 18 PCI_F 9 3V66 [0–1] 25, 26 IOAPIC [0–2] 53, 54, 55 REF [0– ...

Page 3

Function Table [2] SEL133 /100# SEL1 SEL0 Hi 100.227 100 100 TCLK N 133. 133.33 Actual ...

Page 4

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Supply Voltage ..................................................–0.5 to +7.0V Input Voltage .............................................. –0. Operating Conditions [4] Over which Electrical Parameters are Guaranteed Parameter ...

Page 5

Electrical Characteristics Over the Operating Range (continued) Parameter Description I 3.3V Power Supply Cur- DD3 rent I 2.5V Shutdown Current DDPD2 I 3.3V Shutdown Current DDPD3 Switching Characteristics [5] Parameter Output t All Output Duty Cycle 1 t CPU, Rising ...

Page 6

Switching Waveforms Duty Cycle Timing All Outputs Rise/Fall Time OUTPUT t 2 CPU-CPU Clock Skew CPUCLK CPUCLK t 6 IOAPIC-IOAPIC Clock Skew IOAPIC IOAPIC t 8 3V66 - 3V66 Clock Skew 3V66 3V66 t 9 Document #: ...

Page 7

Switching Waveforms (continued) PCI-PCI Clock Skew PCI PCI t 10 CPU - 3V66 Clock Skew CPU 3V66 t 11 3V66 - PCI Clock Skew 3V66 PCI t 12 CPU-IOAPIC Clock Skew CPU t 13 IOAPIC [7, 8] CPU_STOP# Timing CPU ...

Page 8

... Note: Each supply pin must have an individual decoupling capacitor on test circuit at 0.1 µF. Note: All capacitors must be placed as close to the pins as is physically possible. Ordering Information Ordering Code CY28158PVC CY28158PVCT Lead Free CY28158OXC CY28158OXCT Document #: 38-07039 Rev 13, 19, 20, 21, 24, 29, 40, 44, 48, 52 ...

Page 9

... Document #: 38-07039 Rev. *B © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 10

Document Title: CY28158 Spread Spectrum Timing Solution for Serverworks Chipset Document Number: 38-07039 Issue REV. ECN NO. Date ** 107005 08/08/01 *A 122732 12/16/02 *B 237871 See ECN Document #: 38-07039 Rev. *B Orig. of Change Description of Change IKA ...

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