CY28346 Cypress Semiconductor, CY28346 Datasheet - Page 17
CY28346
Manufacturer Part Number
CY28346
Description
Clock Synthesizer with Differential CPU Outputs
Manufacturer
Cypress Semiconductor
Datasheet
1.CY28346.pdf
(20 pages)
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Document #: 38-07331 Rev. *B
AC Parameters
Table 9. Maximum Lumped Capacitive Output Loads
T
T
T
T
T
T
Notes:
27. CPU_STP# and PCI _STP# set-up time with respect to any PCI_F clock to guarantee that the effected clock will stop or start at the next PCI_F clock’s rising edge
28. When crystal meets minimum 40 device series resistance specification.
29. Device is not affected, VTT_PWRGD# is ignored.
PZL
PZL
STABLE
SS
SH
SU
Parameter
VDD Clock Gen
/T
/T
VTT_PWRGD#
Clock Outputs
PZH
PZH
Clock State
Clock VCO
VID (0:3),
SEL (0,1)
PWRGD
Output Enable Delay
(All Outputs)
Output disable delay (all
outputs)
All Clock Stabilization
from Power-up
Stopclock Set-up Time
Stopclock Hold Time
Oscillator Start-up Time
(V
DD
Description
State 0
Off
Off
48MUSB Clock
= V
PCI Clocks
REF Clock
3V66 (0,1)
48MDOT
66B(0:2)
DDA
Clock
= 3.3V ±5%, T
0.2-0.3mS
State 1
Delay
Min.
10.0
1.0
1.0
0
Figure 16. VTT_PWRGD# Timing
66 MHz
A
= 0°C to +70°C) (continued)
Max.
10.0
10.0
VTT_GD#
X
3
Wait for
On
Min.
10.0
1.0
1.0
0
100 MHz
Sample Sels
Max.
10.0
10.0
State 2
3
X
Max Load
Min.
10.0
1.0
1.0
0
30
30
20
10
50
133 MHz
30
Max.
10.0
10.0
X
3
On
State 3
Min.
10.0
1.0
1.0
0
200 MHz
(Note A)
Max.
10.0
10.0
X
3
Units
pF
pF
pF
pF
pF
pF
CY28346
Unit
Page 17 of 20
ms
ms
ns
ns
ns
ns
Notes
10
10
10
27
27
28