AN2153 Freescale Semiconductor / Motorola, AN2153 Datasheet - Page 13

• Manufacturer Part Number: AN2153
• Description: A Serial Bootloader for Reprogramming the MC9S12DP256 FLASH Memory
• Manufacturer: Freescale Semiconductor / Motorola

AN2153
MOTOROLA
NOTE:
initialized. If FDIVLD is clear, it indicates that the register has not been
written to since the part was last reset. Attempting to erase or program
the FLASH without initializing the FCLKDIV register will result in an
access error and the command will not be executed.
A combination of the PRDIV8 and FDIV[5:0] bits is used to divide the
oscillator clock to the 150-kHz to 200-kHz range required by the
FLASH’s state machine. The PRDIV8 bit is used to control a 3-bit
prescaler. When set, the oscillator clock will be divided by eight before
being fed to the 6-bit programmable down counter. Note that if the
oscillator clock is greater than 12.8 MHz, the PRDIV8 bit must be set to
obtain a proper state machine clock source using the FDIV[5:0] bits. The
formulas for determining the proper value for the FDIV[5:0] bits are
shown in
In the formulas, OSCCLK represents the reference frequency present at
the EXTAL pin, NOT the bus frequency or the PLL output. The INT
function always rounds toward zero and FCLK represents the frequency
of the clock signal that drives the FLASH’s state machine.
Erasing or programming the FLASH with an oscillator clock less than
500 kHz should be avoided. Setting FCLKDIV such that the state
machine clock is less than 150 kHz can destroy the FLASH due to high
voltage over stress. Setting FCLKDIV such that the state machine clock
is greater than 200 kHz can result in improperly programmed memory
locations.
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if (OSCCLK > 12.8 MHz)
else
if (PRDIV 8 == 1)
else
FCLKDIV[5:0] = INT((CLK / 1000) / 200)
FCLK = CLK / (FCLKDIV[5:0] + 1)
PRDIV8 = 1
PRDIV8 = 0
CLK = OSCCLK / 8
CLK = OSCCLK
8.
Figure 8. FCLKDIV Formulas
Overview of the MC9S12DP256’s FLASH
Application Note
13