AN2153 Freescale Semiconductor / Motorola, AN2153 Datasheet - Page 24

• Manufacturer Part Number: AN2153
• Description: A Serial Bootloader for Reprogramming the MC9S12DP256 FLASH Memory
• Manufacturer: Freescale Semiconductor / Motorola

Application Note
Startup Code
24
NOTE:
The bootloader startup code implements several setup and initialization
tasks.
The first action performed by the startup code checks the state of pin 6
on port M. If a logic 1 is present, the JMP instruction will continue
execution at the address stored in the reset vector of the secondary
vector table. If a logic 0 is present at pin 6 of port M, execution continues
at the label Boot where the COP watchdog timer is disabled.
After the watchdog timer is disabled, the bootloader copies itself into the
upper 4 K of the on-chip RAM. Execution of the bootloader code from
RAM is necessary so the portion of FLASH block zero not occupied by
the bootloader can be erased and programmed. Notice that only the
code between the labels BootStart and BootLoadEnd is copied into
RAM. This does not include the secondary vector jump table or the
primary interrupt vector addresses since neither is required by the
bootloader. After the copy operation is complete, the RAM is relocated
to overlay the upper 12 K of FLASH memory between $D000 and
$FFFF. Writes to the INITRM register do not go into effect until one bus
clock after the write cycle occurs. This means that the RAM cannot be
accessed at the new address until after this one clock delay. Normally,
the store instruction would simply be followed with a NOP instruction to
ensure that no unintended operations occurred. However, in this case
because the RAM is being moved into the same address space where
the CPU is executing, a CPU free cycle must follow the write cycle.
To understand why the store instruction must use extended addressing
and must be aligned to an even byte boundary, it is necessary to
examine the cycle-by-cycle execution detail of the store instruction.
The STAB instruction using extended addressing requires three clock
cycles when executed from internal MCU memory. These three clock
cycles consist of a P cycle, a w cycle and an O cycle (PwO). The P cycle
is a program word access cycle where program information is fetched as
an aligned 16-bit word. The w cycle is the 8-bit data write. Finally, the O
cycle is an optional cycle that is used to adjust instruction alignment in
the instruction queue. An O cycle can be a free cycle (f) or a program
word access cycle (P). When the first byte of an instruction with an odd
number of bytes is misaligned (at an odd address), the O cycle becomes
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AN2153