CY28378 Cypress Semiconductor, CY28378 Datasheet - Page 5

• Manufacturer Part Number: CY28378
• Description: FTG for Pentium 4 and Intel 845 Series Chipset
• Manufacturer: Cypress Semiconductor

Document #: 38-07519 Rev. **
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface (SDI), various device functions such as
individual clock output buffers, etc. can be individually enabled
or disabled.
The register associated with the SDI initializes to it’s default
setting upon power-up, and therefore use of this interface is
optional. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power
management functions.
Table 3. Command Code Definition
Table 4. Block Read and Block Write Protocol
11:18
20:27
29:36
38:45
2:8
Bit
10
19
28
37
46
....
....
....
....
....
....
1
9
Start
Write = 0
Acknowledge from slave
Command Code – 8 Bit
'00000000' stands for block operation
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Slave address – 7 bits
......................
Data Byte (N–1) –8 bits
Acknowledge from slave
Data Byte N –8 bits
Acknowledge from slave
Stop
Bit
6:0
7
Block Write Protocol
Description
0 = Block read or block write operation
1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these
bits should be ‘0000000’.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write and block read operation from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 3.
The block write and block read protocol is outlined in Table 4
while Table 5 outlines the corresponding byte write and byte
read protocol.
The slave receiver address is 11010010 (D2h).
21:27
30:37
48:55
11:18
39:46
Bit
2:8
10
19
20
28
29
38
47
56
....
....
....
....
1
9
Descriptions
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 Bit
'00000000' stands for block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data byte N from slave – 8 bits
Not Acknowledge
Stop
Block Read Protocol
Description
CY28378
Page 5 of 22