CY28404 Cypress Semiconductor, CY28404 Datasheet - Page 13

• Manufacturer Part Number: CY28404
• Description: CK409-COMPLIANT CLOCK SYNTHESIZER
• Manufacturer: Cypress Semiconductor

Document #: 38-07510 Rev. *B
Watchdog Self Recovery Sequence
This feature is designed to allow the system designer to
change frequency while the system is running and reboot the
operation of the system in case of a hang up due to the
frequency change. When the system sends an SMBus
command requesting a frequency change through the
Dial-a-Frequency Control Registers, it must have previously
sent a command to the Watchdog Timer to select which
time-out stamp the Watchdog must perform, otherwise the
System Self Recovery feature will not be applicable. Conse-
quently, this device will change frequency and then the
Watchdog timer starts timing. Meanwhile, the system BIOS is
VDD Clock Gen
VTT_PWRGD#
PWRGD_VRM
Clock Outputs
FS_A, FS_B
Clock State
Clock VCO
VDDA = 2.0V
Power Off
S0
State 0
Off
Off
Figure 6. Clock Generator Power-up/Run State Diagram
0.2-0.3mS
State 1
Delay
Figure 5. VTT_PWRGD Timing Diagram
VDDA = off
>0.25mS
VTT_PWRGD#
Delay
S1
Wait for
On
VTT_PWRGD# = toggle
VTT_PWRGD# = Low
running its operation with the new frequency. If this device
receives a new SMBus command to clear the bits originally
programmed in the Watchdog Timer bits (reprogram to 0000)
before the Watchdog times out, then this device will keep
operating in its normal condition with the new selected
frequency.
The Watchdog timer will also be triggered if you program the
software frequency select bits (FSEL) to a new frequency
selection. If the Watchdog times out before the new SMBus
reprograms the Watchdog Timer bits to (0000), then this
device will send a low system reset pulse, on SRESET# and
changes WD Time-out bit to “1”.
Operation
Normal
Sample Sels
State 2
S3
Inputs straps
On
State 3
Sample
Enable Outputs
S2
VTT_PWRGD# is ignored
Wait for 1.146ms
Device is not affected,
CY28404
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