CY28409 Cypress Semiconductor, CY28409 Datasheet - Page 11
CY28409
Manufacturer Part Number
CY28409
Description
Clock Synthesizer with Differential SRC and CPU Outputs
Manufacturer
Cypress Semiconductor
Datasheet
1.CY28409.pdf
(18 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY284090C
Manufacturer:
TEXAS
Quantity:
240
Part Number:
CY284090C
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Company:
Part Number:
CY284090CT
Manufacturer:
SONY
Quantity:
35 000
Part Number:
CY284090XC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Part Number:
CY28409OCT
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Part Number:
CY28409ZXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Document #: 38-07445 Rev. *B
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (t
Figure 7.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free-running.
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a high level.
Note:
2.
The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 34 and the other is SMBus byte 0 bit 3. These two inputs are logically
ANDed. If either the external pin or the internal SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus
Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW thereby indicating the device’s stoppable PCI clocks are not running.
SRC 100MHz
SRC 100MHz
PCI_STP#
PCI_STP#
[2]
PCI_F
PCI_F
PCI
PCI
Tsu
Figure 8. PCI_STP# Deassertion Waveform
Tsu
Figure 7. PCI_STP# Assertion Waveform
Tdrive_SRC
SU
). (See
CY28409
Page 11 of 18