CY28411-1 Cypress Semiconductor, CY28411-1 Datasheet
CY28411-1
Related parts for CY28411-1
CY28411-1 Summary of contents
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... DOT96T DOT96C SRCC0 USB_48 SRCT1 SRCC1 VDD_SRC SRCT2 SRCC2 SRCT3 SRCC3 SRC4_SATAT SRC4_SATAC VDD_SRC • 3901 North First Street • San Jose www.DataSheet4U.com CY28411-1 Alviso Chipset PCI REF DOT96 USB_48 PCI2 2 55 PCI_STP CPU_STP# ...
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... LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A, FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD# (active low) assertion, this pin becomes a real-time input for asserting power down (active high). I 14.318-MHz crystal input 14.318-MHz crystal output. CY28411-1 www.DataSheet4U.com Description ,V ,V ILFS_C IMFS_C ...
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... The slave receiver address is 11010010 (D2h). Description Block Read Protocol Bit 1 Start 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 20 Repeat start CY28411-1 www.DataSheet4U.com DOT96 USB 96 MHz 48 MHz 96 MHz 48 MHz 96 MHz 48 MHz 96 MHz 48 MHz Hi-Z Hi-Z REF REF REF REF ...
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... SRC[T/C]6 Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]5 Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]4 Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]3 Output Enable 0 = Disable (Hi-Z Enable CY28411-1 www.DataSheet4U.com Block Read Protocol Description Slave address – 7 bits Read = 1 Acknowledge from slave Byte Count from slave – 8 bits Acknowledge Data byte 1 from slave – ...
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... Free running Stopped with PCI_STP# SRC6 Allow control of SRC[T/C]6 with assertion of PCI_STP PCI_STP Free running Stopped with PCI_STP# SRC5 Allow control of SRC[T/C]5 with assertion of PCI_STP PCI_STP Free running Stopped with PCI_STP# CY28411-1 www.DataSheet4U.com Description Description Description Description Page ...
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... SRC[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted CY28411-1 www.DataSheet4U.com Description Description Description Page ...
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... Crystal Recommendations The CY28411-1 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28411-1 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. ...
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... CL ....................................................Crystal load capacitance CLe ......................................... Actual loading seen by crystal using standard value trim capacitors Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Ci .......................................................... Internal capacitance 1 ) (lead frame, bond wires etc.) CY28411-1 www.DataSheet4U.com Pin Trace 2.8pF Trim 33pF Page ...
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... PD deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Below is an example showing the relationship of clocks coming up. Tstable <1.8nS Tdrive_PWRDN# <300µS, >200mV CY28411-1 www.DataSheet4U.com Page ...
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... CPUT = HIGH and CPUC = LOW. There is no change to the output drive current values during the stopped state. The CPUT is driven HIGH with a current value equal (Iref), and the CPUC signal will be Hi-Z. Figure 5. CPU_STP# Assertion Waveform Tdrive_CPU_STP#,10nS>200mV Figure 6. CPU_STP# Deassertion Waveform CY28411-1 www.DataSheet4U.com 1.8mS Page ...
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... PCI_STP# going LOW Figure 9.) The PCIF clocks will not be affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free running. Tsu Figure 9. PCI_STP# Assertion Waveform Tdrive_SRC Tsu Figure 10. PCI_STP# Deassertion Waveform CY28411-1 www.DataSheet4U.com 1.8mS ). (See SU Page ...
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... Sample Sels Delay VTT_PW RGD# State 1 State 2 On Figure 11. VTT_PWRGD# Timing Diagram S1 VTT_PWRGD# = Low Delay >0.25mS S3 Normal VDD_A = off Operation VTT_PWRGD# = toggle CY28411-1 www.DataSheet4U.com Device is not affected, VTT_PW RGD# is ignored State Sample Inputs straps Wait for <1.8ms Enable Outputs Page ...
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... SDATA, SCLK SDATA, SCLK except internal pull-up resistors, 0 < V except internal pull-down resistors, 0 < – max. load and freq. per Figure 14 PD asserted, Outputs driven PD asserted, Outputs Hi-Z CY28411-1 www.DataSheet4U.com Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD – ...
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... Math averages Figure 14 Math averages Figure 14 See Figure 14. Measure SE Measured at crossing point V OX Measured at crossing point Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX CY28411-1 www.DataSheet4U.com Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10.0 ns – 500 ps – ...
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... Measured at crossing point V Measured at crossing point V Measured from V OL 0.525V Determined as a fraction – T )/( Math averages Figure 14 Math averages Figure 14 See Figure 14. Measure SE Measurement at 1.5V CY28411-1 www.DataSheet4U.com Min. Max. – 125 OX – 300 OX = 0.175 175 700 – 20 ...
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... Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V 60Ω 12Ω 60Ω 12Ω 60Ω 12Ω 60Ω 12Ω 60Ω 12Ω Figure 13. Single-ended Load Configuration CY28411-1 www.DataSheet4U.com Min. Max. 20.83125 20.83542 20.48125 21.18542 8.094 10.036 7.694 9.836 1.0 2.0 – 350 45 55 69.8203 69 ...
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... Figure 14. 0.7V Single-ended Load Configuration Package Type CY28411-1 www.DataSheet4U.com ...
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... GAUGE PLANE 0.110 0.008 0.008 0.016 0.0135 2 C system, provided that the system conforms to the I CY28411-1 www.DataSheet4U.com DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG. 0.508[0.020] 0.762[0.030] 0° ...
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... Document History Page Document Title: CY28411-1 Clock Generator for Intel Document Number: 38-07694 REV. ECN NO. Issue Date ** 246811 See ECN *A 299753 See ECN *B 331934 See ECN Document #: 38-07694 Rev. *B Alviso Chipset Orig. of Change Description of Change RGL New data sheet RGL Corrected the Operating Ambient Temp from 0 to 85° ...