CY29972 Cypress Semiconductor, CY29972 Datasheet - Page 4

• Manufacturer Part Number: CY29972
• Description: 125-MHz Multi-Output Zero Delay Buffer
• Manufacturer: Cypress Semiconductor

Pin Description
Document #: 38-07290 Rev. *D
35, 39, 47, 51
33,37, 45, 49
1, 15, 24, 30,
17, 22, 28,
5, 26, 27
Pin
52
31
14
13
6
7
8
2
3
4
FB_SEL(2:0)
TCLK_SEL
VCO_SEL
REF_SEL
INV_CLK
MR#/OE
PLL_EN
[2]
FB_IN
Name
S
V
S
V
V
DATA
DDC
CLK
DD
SS
PWR
–
–
–
–
–
–
–
–
–
–
–
–
–
I/O
–
–
–
I
I
I
I
I
I
I
I
I
I
Type
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
–
–
–
Feedback select inputs. These inputs select the divide ratio at
FB_OUT output. See
VCO divider select input. When set LOW, the VCO output is divided
by 2. When set HIGH, the divider is bypassed. See
Feedback clock input. Connect to FB_OUT for accessing the PLL.
PLL enable input. When asserted HIGH, PLL is enabled; when LOW,
PLL is bypassed.
Reference select input. When HIGH, the crystal oscillator is selected;
when LOW, TCLK (0,1) is the reference clock.
TCLK select input. When LOW, TCLK0 is selected and when HIGH
TCLK1 is selected.
Master reset/output enable input. When asserted LOW, resets all of
the internal flip-flops and also disables all of the outputs. When pulled
high, releases the internal flip-flops from reset and enables all of the
outputs.
Inverted clock input. When set HIGH, QC(2,3) outputs are inverted.
When set LOW, the inverter is bypassed.
Serial clock input. Clocks data at SDATA into the internal register.
Serial data input. Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in power
management.
3.3 V power supply for output clock buffers.
3.3 V power supply for PLL.
Common ground.
Table 1 on page
Description
1.
Table 1 on page
CY29972
Page 4 of 13
1.
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