CY29973 Cypress Semiconductor, CY29973 Datasheet
CY29973
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CY29973 Summary of contents
Page 1
... MHz. VCO • 198 Champion Court • San Jose CY29973 FB_SEL0 F VC0 12x 0 16x 1 20x 0 16x 1 24x 0 32x 1 40x 10x 12x 0 ...
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... REF_SEL 7 33 TCLK_SEL 8 32 TCLK0 TCLK1 PECL_CLK VDD CY29973 Sync D Q QA0 Frz QA1 QA2 QA3 Sync D Q QB0 Frz QB1 QB2 QB3 Sync D Q QC0 Frz QC1 Sync QC2 ...
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... Serial Data Input. Input data is clocked to the internal register to enable or disable individual outputs. This provides flexibility in power management. 3.3V Power Supply for Output Clock Buffers. 3.3V Supply for PLL. Common Ground. CY29973 Description on page 4 for frequency selections. on page 4 for frequency selections. on page 4 for frequency selections. ...
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... Document #: 38-07291 Rev. *C Zero Delay Buffer When used as a zero delay buffer the CY29973 is likely nested clock tree application. For these applications the CY29973 offers a low voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary clock distribution device to take advantage of its far superior skew performance ...
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... In situations were output frequency relationships are not integer multiples of each other the SYNC output provides a signal for system synchronization. The CY29973 monitors the relationship between the QA and the QC output clocks. It provides a low going pulse, one period in duration, one period prior to the coincident rising edges of the QA and QC outputs. The duration and the placement of the pulse depend on the higher of the QA and QC output frequencies ...
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... Power Management The individual output enable or freeze control of the CY29973 allows the user to implement unique power management schemes into the design. The outputs are stopped in the logic ‘0’ state when the freeze control bits are activated. The serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks ...
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... Q (÷4) – Q (÷6) – Q (÷8) – TCYCLE/2 - 750 2 2 – [9,10] – - 225 QFB =(³ 130 Package Type 52-pin TQFP 52-pin TQFP CY29973 = - 40°C to +85°C (continued) A Min Typ. Max – 225 – – 125 – – 4 – [ 40°C to +85°C A Typ ...
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... Package Drawing and Dimensions Figure 3. 52-Pin Thin Plastic Quad Flat Pack ( 1.0 mm) A52B Document #: 38-07291 Rev. *C CY29973 51-85158-** Page [+] Feedback ...
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... Document History Page Document Title: CY29973 3.3V 125-MHz Multi-Output Zero Delay Buffer Document Number: 38-07291 Orig. of Submission REV. ECN Change ** 111102 BRK *A 122883 RBI *B 200081 RGL *C 2562606 AESA Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...