CY2CC910 Cypress Semiconductor, CY2CC910 Datasheet
CY2CC910
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CY2CC910 Summary of contents
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... The Cypress series of network circuits are produced using advanced 0.35 micron CMOS technology, achieving the industry’s fastest logic and buffers. The Cypress CY2CC910 fanout buffer features one input and 10 outputs ideal for conversion from and to 3.3V, 2.5V, and 1.8V Designed for Data Communications clock management appli- cations, the large fanout from a single input reduces loading on the input clock ...
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... GND VDD GND 20 pin SOIC/SSOP Pin Name Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10 Supply Voltage to Ground Potential (Outputs only) ........................................... –0. Output Voltage.................................... –0. Power Dissipation........................................................ 0.75W CY2CC910 Description Input Ground Power Supply Output DD DD Page [+] Feedback ...
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... Guaranteed Logic Low Level V = Max Max Max (Max Min – Max GND DD OUT V = GND < 4.5V DD OUT CY2CC910 = 25°C) A Pull Up -0.14 -0.12 -0.1 -0.08 -0.06 -0.04 -0.02 Ioh (A) Vdd = 3.3 V Vdd = 2.5 V Vdd = 1.8 V Min Typ Max Unit = –12 mA 2.3 3 0.2 0 5.8 V 0.8 V μ ...
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... Max and – Max and – 0.6V Max DD Input toggling 50% Duty Cycle, Outputs Open = Max DD Input toggling 50% Duty Cycle, Outputs Open MHZ CY2CC910 Min Typ Max Unit 1.8 V 1.6 V 0.65 V 1.6 5.0 V 0.8 V μA 1 μA –1 μA 20 –0.7 –1.2 V – ...
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... OUT See Figure 5 = 3.0V/0. 100 MHz = 2.0V/0.8V See Figure 5 = 2.4V/0. 100 MHz = 1.7V/0.7V See Figure 7 = 1.7V/0. 1.2V/0.4V OUT Description See See See See Description PHL CY2CC910 Min Typ Max Unit 20 ps 160 MHz 650 200 MHz 200 MHz 250 MHz Min ...
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... Description PHL at 3.3V to 2.5V DD Figure 5. Point to Point Load Circuit From Output Under Test [6] Figure 6. Voltage Waveforms – Pulse Duration 0.8VDD 0 V Input t PHL V OH Input VDD CY2CC910 Min Typ Max Unit See Figure 8 1.5 2.7 3.5 ns 1.5 2.7 3.5 ns 0.2 1.5 ns 0.2 1.5 ns Figure 11 0.2 ns See Figure 10 ...
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... V t PHL V OH OUTPUT 0. Figure 11. Output Skew - tsk ( PHL1 PLH1 tsk ( PLH 2 PLH tsk = (P) PLH2 PLH1 PHL2 = 50Ω CY2CC910 [4] t 1.8V w(50-50) 0.9V 0. w(20-80) 1.8V 0. ( PHL PLH VOH 1.5V VOL l l tsk = (P) PHL PLH 3V 1 ...
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... CY2CC910OIT 20-pin SSOP–Tape and Reel CY2CC910OC 20-pin SSOP CY2CC910OCT 20-pin SSOP–Tape and Reel Pb-free CY2CC910OXI 20-pin SSOP CY2CC910OXIT 20-pin SSOP–Tape and Reel CY2CC910OXC 20-pin SSOP CY2CC910OXCT 20-pin SSOP–Tape and Reel Document #: 38-07348 Rev. *C Figure 12. Package Skew - tsk (t) ...
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... Package Drawing and Dimensions Document #: 38-07348 Rev. *C Figure 13. 20-Pin (300-Mil) SOIC S5 (51-85024) CY2CC910 51-85024 *C Page [+] Feedback ...
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... Figure 14. 20-Pin Shrunk Small Outline Package O20 Document #: 38-07348 Rev. *C CY2CC910 51-85077-*C Page [+] Feedback ...
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... Document History Page Document Title: CY2CC910 1:10 Clock Fanout Buffer Document No: 38-07348 Orig. of Submission Rev. ECN NO. Change ** 114318 TSM *A 119148 RGL *B 404287 RGL *C 2595534 CXQ/PYRS Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...