CY2DP1504 Cypress Semiconductor, CY2DP1504 Datasheet

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... CY2DP1504 low-propagation delay 1:4 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DP1504 can select between two separate LVPECL input clock pairs using the IN_SEL pin. The synchronous clock enable function ensures glitch-free output transitions during enable and disable periods. The device has a ...

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... Operating Conditions....................................................... 4 DC Electrical Specifications ............................................ 5 AC Electrical Specifications ............................................ 6 Ordering Information...................................................... 10 Ordering Code Definition ........................................... 10 Package Dimension........................................................ 11 Document Number: 001-56215 Rev. *F Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14 CY2DP1504 Page [+] Feedback ...

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... LVPECL input clock. Active when IN_SEL = Low LVPECL complementary input clock. Active when IN_SEL = Low LVPECL input clock. Active when IN_SEL = High LVPECL complementary input clock. Active when IN_SEL = High No connection Power supply LVPECL complementary output clocks LVPECL output clocks CY2DP1504 Description Page [+] Feedback ...

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... Document Number: 001-56215 Rev. *F Condition Nonfunctional Nonfunctional SS Nonfunctional SS Non functional JEDEC STD 22-A114-B At 1/8 in Condition 2.5-V supply 3.3-V supply Commercial Industrial Power-up time for V DD minimum specified voltage (power ramp must be monotonic). CY2DP1504 Min Max Unit –0.5 4.6 V –0.5 lesser of 4 0.4 DD –0.5 lesser of 4 0.4 DD – ...

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... DD [4] Input = V SS Terminated with 50 Ω [5] – 2.0 DD Terminated with 50 Ω [5] – 2.0 DD CLK_EN has pull-up only IN_SEL has pull-down only Measured at 10 MHz; per pin minimum of greater than 200 mV. ID CY2DP1504 Min Max Unit – – 0 –0.3 – ...

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... Input rise/fall time < 1.5 ns (20% to 80%) Synchronous clock enable – (CLK_EN) switched Low Synchronous clock enable – (CLK_EN) switched High CY2DP1504 Typ Max Unit – 1.5 GHz – 1.5 GHz – – mV – – mV – ...

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... Figure 4. Input to Any Output Pair Propagation Delay Document Number: 001-56215 Rev Figure 3. Output Differential Voltage Figure 5. Output Duty Cycle PERIOD ODC t PERIOD CY2DP1504 )/2 ICM Page [+] Feedback ...

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... Document Number: 001-56215 Rev SK1 t SK1 D Figure 7. RMS Phase Jitter Phase noise Phase noise mark Offset Frequency f2 f1 RMS Jitter ∝ Area Under the Masked Phase Noise Plot Figure 8. Output Rise/Fall Time 80% 80% 20 CY2DP1504 V PP Page [+] Feedback ...

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... CLK_EN IN IN# t SOD Document Number: 001-56215 Rev. *F Figure 9. Synchronous Clock Enable Timing CY2DP1504 t SOE Page [+] Feedback ...

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... Pb-free TSSOP package Number of differential output pairs Base part number Company ID Cypress Document Number: 001-56215 Rev. *F Type Commercial, 0 ° °C Commercial, 0 ° °C Industrial, –40 ° °C Industrial, –40 ° °C CY2DP1504 Production Flow Page [+] Feedback ...

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... Package Dimension Figure 10. 20-Pin Thin Shrunk Small Outline Package (4.40 mm Body) ZZ20 Document Number: 001-56215 Rev. *F CY2DP1504 51-85118 *C Page [+] Feedback ...

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... Unit of Measure °C degree Celsius dBc decibels relative to the carrier GHz giga hertz Hz hertz kΩ kilo ohm µA microamperes µF micro Farad µs microsecond mA milliamperes ms millisecond mV millivolt MHz megahertz ns nanosecond Ω ohm pF pico Farad ps pico second V volts W watts CY2DP1504 Page [+] Feedback ...

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... Document History Page Document Title: CY2DP1504 1:4 LVPECL Fanout Buffer with Selectable Clock Input Document Number: 001-56215 Orig. of Submission Revision ECN Change ** 2782891 CXQ *A 2838916 CXQ *B 3011766 CXQ *C 3017258 CXQ *D 3100234 CXQ *E 3135201 CXQ *F 3090938 CXQ Document Number: 001-56215 Rev. *F Description of Change ...

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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-56215 Rev. *F All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised January 10, 2011 CY2DP1504 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...