CY2DP1510 Cypress Semiconductor, CY2DP1510 Datasheet - Page 3

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CY2DP1510

Manufacturer Part Number
CY2DP1510
Description
1:10 LVPECL Fanout Buffer
Manufacturer
Cypress Semiconductor
Datasheet

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Pinouts
Table 1. Pin Definitions
Document Number: 001-55566 Rev. *G
1, 9, 16, 25, 32
2
3
4
5
6
7
8
10,12,14,17,19,21,
23,26,28,30
11,13,15,18,20,22,
24,27,29,31
Pin No.
V
IN_SEL
IN0
IN0#
V
IN1
IN1#
V
Q(0:9)#
Q(0:9)
EPAD
DD
BB
SS
Pin Name
Power
Input
Input
Input
Output
Input
Input
Power
Output
Output
Figure 1. Pin Diagram – 32-Pin TQFP Package
Q1#
Q0#
Q2#
V
V
Q1
Q2
Q0
Pin Type
DD
DD
25
26
27
28
29
30
31
32
24
1
23
2
Power supply
Input clock select pin. Low-voltage complementary metal oxide
semiconductor (LVCMOS)/low-voltage transistor-transistor-logic (LVTTL).
When IN_SEL = Low, the IN0/IN0# differential input pair is active
When IN_SEL = High, the IN1/IN1# differential input pair is active
LVPECL input clock. Active when IN_SEL = Low
LVPECL complementary input clock. Active when IN_SEL = Low
LVPECL reference voltage output
LVPECL input clock. Active when IN_SEL = High
LVPECL complementary input clock. Active when IN_SEL = High
Ground
LVPECL complementary output clocks
LVPECL output clocks
Exposed paddle. Connect to ground plane for package heat dissipation.
No electrical connection.
22
3
CY2DP1510
21
4
20
5
19
6
18
7
17
8
16
15
14
13
11
10
12
9
Description
V
Q7
Q7#
Q8
Q8#
Q9
Q9#
V
DD
DD
CY2DP1510
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