CY2PP3115 Cypress Semiconductor, CY2PP3115 Datasheet
CY2PP3115
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CY2PP3115 Summary of contents
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... The device features two differential input paths which are multiplexed internally. This mux is controlled by the CLK_SEL pin. The CY2PP3115 may function not only as a differential clock buffer but also as a signal level translator and fanout on ECL/PECL single-ended signal to 15 ECL/PECL differential loads ...
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... FSELA (Asynchronous) FSELB (Asynchronous) FSELC (Asynchronous) FSELD (Asynchronous) CLK_SEL (Asynchronous) MR (Asynchronous) Governing Agencies The following agencies provide specifications that apply to the CY2PP3115. The agency name and relevant specification is listed below. Agency Name JEDEC JESD 51 (Theta JA) JESD 8–2 (ECL) JESD 65–A (skew,jitter) IEEE 1596 ...
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... I = – [ – 2.5V ± pin EE [8] [12 200 orI FastEdge™ Series CY2PP3115 Min. Max. –0.3 4.6 2.5 – –1.620 Vcc–1.220 CC 200 V CC –0.3 V +0.3 CC –0.3 V +0.3 CC 300 –65 +150 –40 ...
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... VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR(AC) range and the input swing lies within the VPP(AC) specification. Violation of VCMR(AC) or VPP(AC) impacts the device propagation delay, device and part-to-part skew. 18. The CY2PP3115 is fully operation up to 1.5 GHz. Document #: 38-07502 Rev.*A ...
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... MHz 50% duty cycle Standard load VCC = 2.5V or 3.3V VCM VCC VPP range 0.1V - 1.3V VEE = 0.0V Figure 1. PECL Waveform Definitions FastEdge™ Series CY2PP3115 Condition Min. – – – – – – – – CLK_SEL 0 1 0.900 0.974 0.979 0.982 ...
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... Document #: 38-07502 Rev.*A PRELIMINARY Figure 2. ECL Differential Waveform Definitions Figure 3. ECL/LVPECL Output FastEdge™ Series CY2PP3115 VO(p-p) VPP / VDIF VOD Page ...
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... Qn Document #: 38-07502 Rev.*A PRELIMINARY tPHL tsk(P) Output pulse skew = | tPLH - tPHL | Figure 5. Output Pulse Skew tsk(0) Qn+m Figure 6. Output-to-output Skew FastEdge™ Series CY2PP3115 VPP / VDIF VO(P-P) VPP / VDIF VO(P-P) VO(P-P) Page ...
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... ohm ohm DUT ohm T CY2PP3115 VTT Figure 7. CY2PP3115 AC Test Reference " " " " ...
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... " " Signaling (LVDS) Interface FastEdge™ Series CY2PP3115 ...
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... Evaluation Material Part Number CY2PP3115AI CY2PP3115AIT Document #: 38-07502 Rev.*A PRELIMINARY Figure 12. Demonstration PCB Package Type 52-Pin TQFP 52-Pin TQFP – Tape and Reel FastEdge™ Series CY2PP3115 Product Flow Industrial, –40° to 85°C Industrial, –40° to 85°C Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY FastEdge™ Series CY2PP3115 51-85131-** Page ...
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... Document History Page Document Title: CY2PP3115 FastEdge™ Series 1:15 Differential Fanout Buffer Document Number: 38-07502 REV. ECN NO. Issue Date ** 122042 02/12/03 *A 131090 11/21/03 Document #: 38-07502 Rev.*A PRELIMINARY Orig. of Change Description of Change RGL New Data Sheet RGL Supplied numbers for all specs with TBD after characterization FastEdge™ ...