CY2SSTU877 Cypress Semiconductor, CY2SSTU877 Datasheet

CY2SSTU877

Manufacturer Part Number

CY2SSTU877

Description

10-Output JEDEC-Compliant Zero Delay Buffer

Manufacturer

Cypress Semiconductor

Datasheet

1.CY2SSTU877.pdf (9 pages)

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Cypress Semiconductor Corporation

Document #: 38-07575 Rev. *B

Features

Functional Description

The CY2SSTU877 is a high-performance, low-skew, low-jitter

zero delay buffer designed to distribute differential clocks in

high-speed applications. The CY2SSTU877 generates ten

differential pair clock outputs from one differential pair clock

input. In addition, the CY2SSTU877 features differential

feedback clock outputs and inputs. This allows the

CY2SSTU877 to be used as a zero delay buffer. When used

as a zero delay buffer in nested clock trees, the CY2SSTU877

locks onto the input reference and translates with near zero

delay to low-skew outputs.

Block Diagram

• Operating frequency: 125 MHz to 500 MHz

• Supports DDRII SDRAM

• Ten differential outputs from one differential input

• Spread-Spectrum-compatible

• Low jitter (cycle-to-cycle): < 40 ps

• Very low skew: < 40 ps

• Power management control input

• 1.8V operation

• Fully JEDEC-compliant

• 52-ball BGA and a 40-pin MLF (QFN)

1.8V, 500-MHz, 10-Output JEDEC-Compliant

•

3901 North First Street

PRELIMINARY

This phase-locked loop (PLL) clock buffer is designed for a

VDD of 1.8V, an AVDD of 1.8V and differential data input and

output levels. Package options include a plastic 52-ball

VFBGA and a 40-pin MLF (QFN). The device is a zero delay

buffer that distributes a differential clock input pair (CK, CK#)

to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one

differential pair feedback clock outputs (FBOUT, FBOUT#).

The input clocks (CK, CK#), the feedback clocks (FBIN,

FBIN#), the LVCMOS (OE, OS), and the analog power input

(AVDD) control the clock outputs.

The PLL in the CY2SSTU877 clock driver uses the input

clocks (CK, CK#) and the feedback clocks (FBIN, FBIN#) to

provide high-performance, low-skew, low-jitter output differ-

ential clocks (Y[0:9], Y#[0:9]). The CY2SSTU877 is also able

to track Spread Spectrum Clocking (SSC) for reduced EMI.

When AVDD is grounded, the PLL is turned off and bypassed

for test purposes. When both clock signals (CK, CK#) are logic

low, the device will enter a low-power mode. An input logic

detection circuit on the differential inputs, independent from

the input buffers, will detect the logic low level and perform a

low-power state where all outputs, the feedback, and the PLL

are OFF. When the inputs transition from both being logic low

to being differential signals, the PLL will be turned back on, the

inputs and outputs will be enabled and the PLL will obtain

phase lock between the feedback clock pair (FBIN, FBIN#)

and the input clock pair (CK, CK#) within the specified stabili-

zation time t

Pin Configuration

AG N D

VD DQ

A VD D

VD DQ

•

C LK #

G N D

C LK

Y2#

AGND

AVDD

Y 2

CK#

Y1#

Y2#

Y3#

San Jose

VDDQ

GND

Y4#

52 BGA

C Y 2S S T U 877

VDDQ

CA 95134

GND

Y0#

Zero Delay Buffer

40 Q FN

Revised January 19, 2005

VDDQ

GND

Y5#

CY2SSTU877

VDDQ

GND

•

Y5#

408-943-2600

FBOUT#

FBOUT

FBIN#

FBIN

Y6#

Y7#

Y8#

Y7#

VD D Q

FB IN

FB IN #

FB O U T#

FB O U T

VD D Q

O E

O S

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CY2SSTU877 Summary of contents

Page 1

... In addition, the CY2SSTU877 features differential feedback clock outputs and inputs. This allows the CY2SSTU877 to be used as a zero delay buffer. When used as a zero delay buffer in nested clock trees, the CY2SSTU877 locks onto the input reference and translates with near zero delay to low-skew outputs. ...

Page 2

... Buffered output of input clock, CLK CLK CLK Lz,Y7 Active Lz,Y7 Active Condition CY2SSTU877 Description Outputs Y# FBOUT FBOUT Lz,Y7# Active Lz,Y7# Active Reserved Min ...

Page 3

... – – Description Y[0:9], Y#[0:9], FBOUT, FBOUT# CLK, CLK#, FBIN, FBIN# OE (Input Capacitance of CK, CK#, FBIN, FBIN VDDQ or GND Ci(delta) (CK, CK#, FBIN, FBIN VDDQ or GND Description CY2SSTU877 Min. Max. –0.5 V DDQ –0.5 V DDQ –65 150 –0.5 2.5 –50 50 –50 50 –50 50 –100 100 Min ...

Page 4

... PRELIMINARY (continued) Description Conditions Above 270 MHz Below 270 MHz Average 1000 cycles (Y[0:9], Y#[0:9] @ 500 MHz any Y/ any Y/Y# Figure 1. Test Loads for Timing Measurement #1 Figure 2. Test Loads for Timing Measurement #2 CY2SSTU877 Min. Max. Unit – – – – ...

Page 5

... Document #: 38-07575 Rev. *B PRELIMINARY Figure 3. Cycle to Cycle Jitter Figure 4. Period Jitter Figure 5. Half Period Jitter CY2SSTU877 Page ...

Page 6

... Document #: 38-07575 Rev. *B PRELIMINARY Figure 6. Static Phase Offset Figure 7. Dynamic Phase Offset Figure 8. Output Skew CY2SSTU877 Page ...

Page 7

... CY2SSTU877BVC-XX CY2SSTU877BVC-XXT CY2SSTU877LFI-XX CY2SSTU877LFI-XXT CY2SSTU877BVI-XX CY2SSTU877BVI-XXT Lead-free CY2SSTU877LFXC-XX CY2SSTU877LFXC-XXT CY2SSTU877BVXC-XX CY2SSTU877BVXC-XXT CY2SSTU877LFXI-XX CY2SSTU877LFXI-XXT CY2SSTU877BVXI-XX CY2SSTU877BVXI-XXT Document #: 38-07575 Rev. *B PRELIMINARY Figure 9. Time Delay Between OE and Clock Output (Y, Y) Figure 10. Input/Output Slew Rates Package Type 40-pin QFN 40-pin QFN – Tape and Reel 52-pin VFBGA 52-pin VFBGA– ...

Page 8

... TOP VIEW 4.50±0.10 40-lead QFN LF40A SIDE VIEW 0.08[0.003] 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 0°-12° C SEATING PLANE CY2SSTU877 BOTTOM VIEW A1 CORNER Ø0. Ø0. Ø0.30±0.05(52X ...

Page 9

... Document History Page Document Title:CY2SSTU877 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Document Number: 38-07575 Rev. ECN No. Issue Date ** 129198 08/22/03 *A 204389 See ECN *B 310414 See ECN Document #: 38-07575 Rev. *B PRELIMINARY Orig. of Change Description of Change RGL New Data Sheet RGL Added more Information. Deleted 4 rows from the bottom of the Pin description ...

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