CY2SSTV857-32 Cypress Semiconductor, CY2SSTV857-32 Datasheet - Page 4

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CY2SSTV857-32

Manufacturer Part Number
CY2SSTV857-32
Description
Differential Clock Buffer/Driver DDR400/PC3200-Compliant
Manufacturer
Cypress Semiconductor
Datasheet
www.DataSheet4U.com
Document #: 38-07557 Rev. *E
CLK#
CLK
represents a capacitive load
Yx or FBIN
DDR _SDRAM
Yx
Output load capacitance for 2 DDR-SDRAM Loads: 5 pF< CL< 8 pF
CLKIN
120
Ohm
120
Ohm
Figure 2. Propagation Delay Time t
Figure 3. Cycle-to-cycle Jitter
Figure 4. Clock Structure # 1
PLL
FBIN
FBIN#
t
pd
t
C(n)
FBOUT#
FBOUT
= 2.5"
PLH
t
0.3"
C(n+1)
, t
= 0.6" (Split to Terminator)
PHL
SDRAM
SDRAM
DDR -
DDR -
VCP
VTR
CY2SSTV857-32
120
Ohm
Page 4 of 9

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