CY2SSTV8575 Cypress Semiconductor, CY2SSTV8575 Datasheet

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CY2SSTV8575

Manufacturer Part Number
CY2SSTV8575
Description
Differential Clock Buffer/Driver
Manufacturer
Cypress Semiconductor
Datasheet

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Features
Cypress Semiconductor Corporation
Document #: 38-07458 Rev. **
• Operating frequency: 60 MHz to 170 MHz
• Supports 266-MHz DDR SDRAM
• 5 differential outputs from 1 differential input
• Spread Spectrum compatible
• Low jitter (cycle-to-cycle): < 75
• Very low skew: < 100 ps
• Power Management Control input
• High-impedance outputs when input clock < 20 MHz
• 2.5V operation
• 32-pin TQFP JEDEC MS-026 C
Block Diagram
CLK
CLK#
AVDD
FBIN
OE
FBI
N
#
23
8
21
22
5
6
Powerdown
Test and
PLL
Logic
12
16
27
28
30
18
19
11
15
31
2
1
Y0
Y0#
Y1
Y1#
Y2
Y2#
Y3
Y3#
Y4
Y4#
FBOUT#
FBOUT
3901 North First Street
Description
The CY2SSTV8575 is a high-performance, low-skew, low jitter
zero-delay buffer designed to distribute differential clocks in
high-speed applications. The CY2SSTV8575 generates five
differential pair clock outputs from one differential pair clock
input. In addition, the CY2SSTV8575 features differential
feedback clock outputs and inputs. This allows the
CY2SSTV8575 to be used as a zero-delay buffer.
When used as a zero-delay buffer in nested clock trees, the
CY2SSTV8575 locks onto the input reference and translates
with near zero delay to low-skew outputs.
VDDQ
VDDQ
VSS
VSS
Y3#
Y4#
Y4
Y3
Pin Configuration
Differential Clock Buffer/Driver
24 23 22 21 20 19 18 17
San Jose
1 2 3 4 5 6 7 8
CY2SSTV8575
JEDEC MS-026 C
TQFP-32
CA 95134
CY2SSTV8575
Revised October 30, 2002
AVSS
Y2#
VDDQ
Y1#
VSS
Y2
VSS
Y1
408-943-2600

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CY2SSTV8575 Summary of contents

Page 1

... In addition, the CY2SSTV8575 features differential feedback clock outputs and inputs. This allows the CY2SSTV8575 to be used as a zero-delay buffer. When used as a zero-delay buffer in nested clock trees, the CY2SSTV8575 locks onto the input reference and translates with near zero delay to low-skew outputs. Pin Configuration 2 ...

Page 2

... During disable (OE = 0), the PLL is powered down. 0.0V Ground Common Ground 0.0V Analog Ground Analog Ground CLK < 20 MHz Hi-Z CY2SSTV8575 Description OUTPUTS Y# FBOUT FBOUT Hi-Z Hi-Z HI-Z PLL ...

Page 3

... Zero Delay Buffer When used as a zero delay buffer the CY2SSTV8575 will likely nested clock tree application. For these applications the CY2SSTV8575 offers a differential clock input pair as a DDR _SDRAM ...

Page 4

... VDD www.DataSheet4U.com Figure 3. Differential Signal Using Direct Termination Resistor Governing Agencies The following agencies provide specifications that apply to the CY2SSTV8575. The agency name and relevant specification is listed below; Agency Name JEDEC Note: 2. Output load capacitance for 4 DDR-SDRAM loads < CL < 16 pF. ...

Page 5

... Temperature = 0°C to +85°C) DDO Conditions [ 2.375V, I DDQ 2.375V, I DDQ 2.375V, V DDQ V = 2.375V, V DDQ [4] ALL 170 MHz DDQ CLK/CLK# 20 MHz CY2SSTV8575 and V should be constrained to the in out < < Voltage) in out DD DDQ . DDQ Min. Max. –0.3 3.5 2.38 2.63 – ...

Page 6

... MHz to 100 MHz 101 MHz to 170 MHz 20 20 [9] All outputs equally loaded CLK to Y CLK to Y [8] All outputs [8] All outputs All outputs @ 66 MHz All outputs @ 66 MHz CY2SSTV8575 Min. Typ. Max. Unit 60 – 170 MHz 40 – [5,6] Min. Typ. ...

Page 7

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Type 32-Lead Thin Plastic Quad Flatpack 1.0 mm A32 CY2SSTV8575 Product Flow Commercial Commercial ...

Page 8

... Document History Page Document Title: CY2SSTV8575 Differential Clock Buffer/Driver Document #: 38-07458 Issue Rev. ECN No. Date ** 120711 10/31/02 www.DataSheet4U.com Document #: 38-07458 Rev. ** Orig. of Change Description of Change RGL New Data Sheet CY2SSTV8575 Page ...

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