CY2XF32 Cypress Semiconductor, CY2XF32 Datasheet - Page 2

• Manufacturer Part Number: CY2XF32
• Description: High Performance CMOS Oscillator
• Manufacturer: Cypress Semiconductor

Pinouts
Table 1. Pin Definitions – 6-pin Ceramic LCC
Functional Description
The FS0 and FS1 pins select between four different output
frequencies, as shown in
common application for this feature. One frequency is used for
the standard operating mode of the device, while the other
frequencies are available for margin testing, either during
product development or in system manufacturing test.
Table 2. Frequency Select
When changing the output frequency, the frequency transition is
not guaranteed to be smooth. There can be frequency excur-
sions beyond the start frequency and the new frequency.
Document Number: 001-53147 Rev. *D
1
2, 5
4
6
3
Pin
FS1
0
0
1
1
FS1, FS0
OE/PD#
CLK
VDD
VSS
Name
FS0
0
1
0
1
CMOS Input
CMOS Input
CMOS Output
Power
Power
Table
I/O Type
Frequency 0
Frequency 1
Frequency 2
Frequency 3
2. Frequency margining is a
Output Frequency
Output Enable or Power-down: Functionality is a programming option; see
Table 4
Frequency Select.
Clock Output.
Supply Voltage: 2.5 V or 3.3 V.
Ground.
Figure 1. Pin Diagram – 6 Pin Ceramic LCC
for details.
OE/PD#
VSS
FS1
1
2
3
Glitches and runt pulses are possible, and time must be allowed
for the PLL to relock.
Pin 1 is programmed to function as either OE (output enable) or
PD# (power-down, active low). The OE function is used to enable
or disable the CLK output very quickly, but it does not reduce
core power consumption. The PD# function puts the device into
a low power state, but the wake up takes longer because the PLL
must reacquire lock. Details are shown in
Table 3. Output Enable Operation
Table 4. Power-down Operation
6
5 FS0
4
PD#
OE
0
1
0
1
VDD
CLK
Description
PLL & Xtal Oscillator
PLL & Xtal Oscillator
Active
Active
Active
Off
Table 3
Output Buffer
Output Buffer
Table 3
CY2XF32
and
Off
On
Off
On
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Table
and
4.
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