CY2XP24 Cypress Semiconductor, CY2XP24 Datasheet - Page 7

• Manufacturer Part Number: CY2XP24
• Description: Crystal to LVPECL Clock Generator
• Manufacturer: Cypress Semiconductor

Application Information
Power Supply Filtering Techniques
As in any high speed analog circuitry, noise at the power supply
pins can degrade performance. To achieve optimum jitter
performance, use good power supply isolation practices.
Figure 8
flows through pin 1, the resistance and inductance between this
pin and the supply is minimized. A 0.01 or 0.1 µF ceramic chip
capacitor is also located close to this pin to provide a short and
low impedance AC path to ground. A 1 to 10 µF ceramic or
tantalum capacitor is located in the general vicinity of this device
and may be shared with other devices.
Figure 8. Power Supply Filtering
Termination for LVPECL Output
The CY2XP24 implements its LVPECL driver with a current
steering design. For proper operation, it requires a 50 ohm dc
termination on each of the two output signals. For 3.3 V
operation, this data sheet specifies output levels for termination
to V
= 2.5 V operation, or it can be terminated to V
it is also possible to terminate with 50 ohms to ground (V
the high and low signal levels differ from the data sheet values.
Termination resistors are best located close to the destination
device. To avoid reflections, trace characteristic impedance (Z
should match the termination impedance.
standard termination scheme.
Document #: 001-15705 Rev. *G
DD
–2.0 V. This termination voltage can also be used for V
illustrates a typical filtering scheme. Because all current
(Pin 1)
(Pin 8)
V DD
V DD
F
CLK#
0.01 µF
CLK
3.3V
10µ F
DD
Figure 9
-1.5 V. Note that
Figure 7. Output Duty Cycle
shows a
T
SS
PERIOD
), but
DD
0
)
T
PW
Figure 9. LVPECL Output Termination
Crystal Input Interface
The CY2XP24 is characterized with 18 pF parallel resonant
crystals. The capacitor values shown in
determined using a 25 MHz 18 pF parallel resonant crystal and
are chosen to minimize the ppm error. Note that the optimal
values for C1 and C2 depend on the parasitic trace capacitance
and are therefore layout dependent.
Figure 10. Crystal Input Interface
CLK#
CLK
18 pF Parallel
Crystal
X1
T
DC
=
Z0 = 50
Z0 = 50
T
T
PERIOD
PW
30 pF
27 pF
C1
C2
XOUT
XIN
84
125
Device
3.3V
84
125
CY2XP24
Figure 10
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