AN2417 Freescale Semiconductor / Motorola, AN2417 Datasheet - Page 6

• Manufacturer Part Number: AN2417
• Description: PCMCIA and Compact Flash Interface for the MC9328MX1 and MC9328MXL Application Processors Application Note
• Manufacturer: Freescale Semiconductor / Motorola

Introduction
1.6.4 Control Signal
OE# WE# IORD# IOWR#
Output Enable signal OE# is generated by host to indicate the access cycle is a read cycle, and this signal is
used in memory mode. In I/O mode, separate signal IORD# is used to indicate a read cycle. Similarly,
WE# is used in memory mode and IOWR# for I/O mode to indicate a write access cycle. Since DragonBall
MX do not have separate output enable pin for I/O access cycle, address pin A23 is used to select whether
the access cycle is an memory access or I/O access.
The Compact Flash specification define minimum setup time and hold time for the OE#, WE#, IORD# and
IOWR# signal that may not met by CS5. For this reason, glue logic is necessary to produce the delay to
meet the setup and hold time requirement which is discussed under the section Timing Characteristic.
CE1# CE2#
CE1# and CE2# are used to select the card and to indicate the card whether a byte or word operation is
being performed. CE2# access the odd byte of word and CE1# access the even or odd byte of the word
depends on A0. A multiplexing scheme allow 16 bit or 8 bit data to be transferred in the access cycle and is
shown in the following table.
In EIM, EB3 signal control the enable of D7:D0 and EB2 signal control the enable of D15:D8. Hence
CE1# signal is the logic OR output of EB3 and CS5 while CE2# signal is the logic OR output of EB2 and
CS5.
READY (IREQ)
The ready signal is set high when Compact Flash is ready to accept a new data transfer operation and held
low when the card is busy. This signal is specially useful at power up and reset by the reset pin. At power
up and reset, the RDY/BSY signal is held low until Compact Flash has complete its reset function. No
access to card should be made during this time.
If the Compact Flash is configured to work in I/O mode, the signal is used as interrupt request. This line is
strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. The mode of
interrupt can be select in the Configuration Option Register in attribute memory. When the Interrupt
function is used, the GPIO PA18 should be set as interrupt accordingly.
RESET
The reset pulse is generated by setting GPIO PB17 high, running a delay loop for a minimum duration of
10us and setting GPIO PB 17 low. This reset is necessary at power up after 1ms of power supply.
WAIT
The WAIT signal from compact flash is connect to DTACK of CS5.
6
No access
8/16 bit (even byte)
8 bit (odd byte)
16 bit (odd byte only)
16 bit (even & odd byte)
Addressing Mode
Freescale Semiconductor, Inc.
For More Information On This Product,
MC9328MX1/MXL Application Note
Engineering Draft / Preliminary
Go to: www.freescale.com
CE1#
1
0
0
1
0
Table 4.
CE2#
1
1
1
0
0
A0
X
X
X
0
1
Odd Byte
Odd Byte
D15:D8
High-Z
High-Z
High-Z
Even Byte
Even Byte
Odd Byte
High-Z
High-Z
D7:D0
MOTOROLA