AN2528 Freescale Semiconductor / Motorola, AN2528 Datasheet - Page 13

• Manufacturer Part Number: AN2528
• Description: Standard Space Vector Modulation TPU Function Set
• Manufacturer: Freescale Semiconductor / Motorola

MOTOROLA
Standard Space Vector Modulation TPU Function Set (svmStd)
The MPW is written by the CPU. The MPW depends on the whole TPU unit
configuration, especially the lengths of the longest states of other functions,
and their priorities, running on the same TPU. The MPW has to be correctly
calculated at the time the whole TPU unit is configured.
When svmStd_top and svmStd_bottom are running alone on one TPU, the
minimum pulse width can be calculated according to
the worst case timing. The bottom channel low to high transition runs the HL
state that sets the following high to low transition. The HL state lasts 6 IMB
clock cycles (see
(TST), which takes 10 IMB clock cycles. So the time necessary to set the next
transition on the bottom channel is 16 IMB clock cycles. In addition, there is a
latency between the low to high transition and the start of the HL state. The top
channel state LH_C5, which is serviced at the time, causes the latency. The
LH_C5 state lasts 28 IMB clock cycles (see
Freescale Semiconductor, Inc.
bottom channel
bottom channel
top channel
top channel
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0.9
0.9
0.8
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0.7
0.7
0.6
0.6
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
1
1
0
0
Standard Space Vector Modulation Technique - limitation
Standard Space Vector Modulation Technique - limitation
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0
0
0
center_time
center_time
Table
Figure 6. Timing of the worst case
60
60
60
10). Each state is preceded by the Time Slot Transition
Figure 5. Effect of limitation
120
120
120
180
180
180
Table
240
240
240
DT
DT
9). Its time slot transition is
LH_C5
LH_C5
latency
latency
Figure
300
300
300
MPW
MPW
Detailed Function Description
Phase A
Phase A
Phase A
Phase B
Phase B
Phase B
Phase C
Phase C
Phase C
HL
HL
6. This illustrates
360
360
360
AN2528/D
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