AN2528 Freescale Semiconductor / Motorola, AN2528 Datasheet - Page 14

• Manufacturer Part Number: AN2528
• Description: Standard Space Vector Modulation TPU Function Set
• Manufacturer: Freescale Semiconductor / Motorola

AN2528/D
14
top channel
top channel
bottom channel
bottom channel
time slot sequence
time slot sequence
Standard Space Vector Modulation TPU Function Set (svmStd)
TST
TST
10 IMB clock cycles. The service starts immediately after the top channel high
to low transition, which occurs at a period of DT before the bottom channel low
to high transition (see
IMB clock cycles – DT. The svmStd functions are designed so that no other
svmStd state can request service at this time. The MPW, in the case when only
svmStd functions are running on one TPU, is then
and is a minimum at least 16 IMB clock cycles (when latency = 0).
Note that the MPW, as well as the DT, are not entered into the parameter RAM
in IMB clock cycles, but in TCR1 clock cycles. It is recommended for the
svmStd function that the TCR1 clck is configured for its maximum speed, which
is the IMB clock divided by 2. In this case the MPW = 27 – DT, with a minimum
value of 8.
When other functions are running together on the same TPU as the svmStd
functions, the latency could be lengthened. To maintain sufficiently high
performance of svmStd, it is recommended that the following rules are followed
to configure the TPU:
In this instance, one of the two worst case timing cases can happen. These are
illustrated in
= 28 IMB clock cycles + 10 IMB clock cycles – DT + 16 IMB clock cycles =
•
•
Freescale Semiconductor, Inc.
Figure 7. Worst case timing – case one
For More Information On This Product,
H
H
assign svmStd PWM channels high priority
assign svmStd PWM functions on low channel numbers so that no other
function with high priority is assigned a channel with a lower number
DT
DT
Figure 7
TST
TST
Go to: www.freescale.com
M
M
Figure
and
TST+4
TST+4
latency + 16 IMB clock cycles =
= 54 IMB clock cycles – DT
Figure
6), so that the latency is 28 IMB clock cycles + 10
LH_C5
LH_C5
latency
latency
H
H
8. Which case occurs depends on the DT.
MPW
MPW
TST
TST
L
L
TST+4
TST+4
HL
HL
H
H
MOTOROLA