AN2548 Freescale Semiconductor / Motorola, AN2548 Datasheet - Page 16

• Manufacturer Part Number: AN2548
• Description: Serial Monitor Program for HCS12 MCUs
• Manufacturer: Freescale Semiconductor / Motorola

AN2548/D
IF EndOfApplication >= $F780
//ROM_C000 = READ_ONLY
Monitor Mode
versus Run Mode
16
ENDIF
ROM_C000 = READ_ONLY
FAIL "Application code overflows into Monitor area"
For assembly programs — In the CodeWarrior assembler, the following
definition may be added to generate an automatic error if this occurs:
The application just needs to define the EndOfApplication label to reference the
end of the application code.
For C programs in the CodeWarrior environment, FLASH settings for the upper
bank should be modified in the .prm file. Shown below is an example:
Change to:
At any given time, the target MCU is operating in either monitor mode or run
mode. Monitor mode refers to the mode of operation where the target MCU is
executing code within the monitor and keeps active control waiting for
additional commands through the serial interface. Run mode refers to the mode
of operation where the target MCU is executing the user application program.
Some monitor commands such as Read_Byte and Write_Byte can be
executed while the target MCU is in run mode. In this case, an SCI0 interrupt
causes the monitor to temporarily gain control to decode and execute the
requested command. When the command is completed, the monitor
automatically returns control to the user application program. Throughout such
a sequence, the target MCU is said to be in run mode even though software in
the monitor is executed to complete the requested command.
The HALT command causes an SCI0 interrupt which causes the CPU registers
to be pushed onto the stack. The ISR for SCI0 then sets the run mode flag
(even though this flag will be cleared again if the command that caused the
SCI0 interrupt turns out to be the HALT command).
Breakpoints use the SWI exception (the TRACE1 command also uses this
hardware breakpoint), which is not blocked when the I bit in the CCR is set. This
implies that TRACE1 and breakpoints always work independent of what the
user program does to the I bit. Other commands use the SCI0 interrupt. These
other commands cannot execute unless the user program clears the I bit.
There are some cases where it would be natural for a user program to set the
0xC000 TO 0xFF7F; /* upper bank of 16K FLASH */
0xC000 TO 0xF77F; /* upper bank of 16K FLASH */
4. Application code should exclude the $F780–$FF7F memory.
Freescale Semiconductor, Inc.
For More Information On This Product,
Serial Monitor Program for HCS12 MCUs
Go to: www.freescale.com
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