AN2548 Freescale Semiconductor / Motorola, AN2548 Datasheet - Page 18

• Manufacturer Part Number: AN2548
• Description: Serial Monitor Program for HCS12 MCUs
• Manufacturer: Freescale Semiconductor / Motorola

AN2548/D
Vector Redirection
18
NOTE:
SpSub on the stack. The next line preloads A with a mask corresponding to the
CBEIF bit which will be used to complete the FLASH command.
At this point if the monitor program is active, the I bit in the CCR is already set
to mask interrupts; however, since this routine can also be called as a utility
subroutine from a user program, the I bit may or may not be set at the time
DoOnStack is called. The next two lines save the CCR (and the I bit) for
restoration after the JSR calls the SpSub routine.
The JSR ,x instruction calls the copy of SpSub that is now located on the stack.
The SpSub subroutine was written in a position-independent manner so it could
be copied to a new location (on the stack) and would still execute as expected.
SpSub is such a short subroutine that it was easy to make it position
independent.
SpSub completes the FLASH command by writing 1 to the CBEIF bit in FSTAT.
The series of NOPs in the routine is to used to ensure that the FLASH state
machine has registered the command before polling begins. This delay is
required so the internal FLASH command sequencer can properly update the
CBEIF and CCIF flags in FSTAT. Execution stays in the ChkDone loop until the
command finishes (CCIF becomes set). At this point, the FLASH is back in the
memory map and we can return to DoOnStack (which is in FLASH). The RTS
in the SpSub returns to the DoOnStack routine.
Due to the RTS (in lieu of an RTC instruction), any user calls to this routine from
banked memory are prohibited. This means that user access to this routine
must be called from the non-banked areas of FLASH ($4000 or $C000 areas).
The CCR can be saved if needed, but not the interrupt state. CCR should be
restored (as well as the interrupt state), and the stack used for the SpSub is
deallocated. Next the FSTAT register is read and masked for the FACCERR
and FPVIOL violations are recorded to be returned to the calling program. The
IX register is then restored with the status of the routine preserved so that a
simple BEQ or BNE can be used to check for errors after returning to the main
program.
This monitor uses a software pseudo-vector mechanism that is traditionally
used in ROM monitors. Because the monitor resides at $F800–$FFFF, and this
2-Kbyte block is protected, when an interrupt occurs, the vector is fetched from
$FF80–$FFFE as normal, but is redirected to the pseudo-vector table located
at $F780–$F7FE. This vector redirection mechanism places the pseudo-vector
interrupt vectors in unprotected space so the user can control the contents.
Because the real vectors are in protected space, it is not possible for a user to
unintentionally erase the real vectors.
After power-on, reset, or while the monitor is active, due to ISR or startup entry
the I bit in the CCR is set. This prevents interrupts from being recognized so
Freescale Semiconductor, Inc.
For More Information On This Product,
Serial Monitor Program for HCS12 MCUs
Go to: www.freescale.com
MOTOROLA