AN2866 Freescale Semiconductor / Motorola, AN2866 Datasheet - Page 3

• Manufacturer Part Number: AN2866
• Description: Migrating from the MC68332 to the ColdFire MCF523x
• Manufacturer: Freescale Semiconductor / Motorola

The MCF523x core includes the following:
System control options and capabilities offered in the MCF523x are the following:
Freescale Semiconductor
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— 10/100 Fast Ethernet (media access) controller (FEC)
— Controller Area Network (CAN) controller
— I
— 4-channel Direct Memory Access controller (DMA)
— 4 DMA-supported 32-bit timer modules
— Synchronous/asynchronous Dynamic Random Access Memory (SDRAM) controller
— Optional hardware cryptography accelerator modules
Version 2 ColdFire core providing up to 144 Dhrystone 2.1 MIPS at 150 MHz
— Processor core runs at twice the bus frequency
— Implements the ColdFire Instruction Set Architecture, ISA_A+, with extensions to support the
— Illegal instruction decode that allows for 68K emulation support
System debug support
— Background debug mode (BDM) for in-circuit debugging
— Real time debug support, with two user-visible hardware breakpoint registers (PC and address
— Real time trace for determining dynamic execution path
— New fully-integrated eTPU debug support. This provides access to the eTPU debug registers
The MCF523x’s Enhanced Multiply-Accumulate controller (EMAC) unit provides a common set
of simple DSP operations, and speeds the execution of the integer multiply instructions for both
signed and unsigned operands in the ColdFire core.
— Multiplies of 16x16 and 32x32 with 32-bit accumulates are supported. The EMAC unit is
— The OEP can issue a 16x16 multiply with a 32-bit accumulation and fetch a 32-bit operand in
A hardware divide module is also coupled to the core’s OEP, which allows the processor to
support signed divides, unsigned divides, and remainder instructions.
A base address register that provides relocation of internal resources
Two interrupt controllers that support seven programmable interrupt levels for internal peripheral
interrupts and seven external interrupt pins; each interrupt level has eight programmable and one
fixed priority levels
A software watchdog timer to prevent erratic operation caused by runaway code execution
user stack pointer, and four new instructions for improved bit processing
with optional data) that can be configured for a 1- or 2- level triggered
via the standard ColdFire BDM serial interface or the processor WDEBUG instruction and
run/halt triggering capability between eTPU and ColdFire BDM.
tightly coupled to the Operand Execution Pipeline (OEP) and features a four-stage execution
pipeline.
the same cycle.
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C communication controller
Migrating from the MC68332 to the ColdFire
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MCF523x, Rev. 1.0
Comparison Overview
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