AD8197 Analog Devices, AD8197 Datasheet - Page 17

• Manufacturer Part Number: AD8197
• Description: 4:1 HDMI/DVI Switch with Equalization
• Manufacturer: Analog Devices

Preliminary Data Sheet
GENERAL CASE
READ PROCEDURE
To read data from the AD8197 register set, an I
as a microcontroller) needs to send the appropriate control
signals to the AD8197 slave device. The signals are controlled
by the I
the procedure, see Figure 30. The steps for a read procedure are
as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Wait for the AD8197 to acknowledge the request.
11. The AD8197 serially transfers the data (eight bits) held in
12. Acknowledge the data from the AD8197.
13. Perform one of the following:
Send a start condition (while holding the I2C_SCL line
high, pull the I2C_SDA line low).
Send the AD8197 part address (seven bits). The upper four
bits of the AD8197 part address are the static value [1001]
and the three LSBs are set by Input Pin I2C_ADDR2, Input
Pin I2C_ADDR1, and Input Pin I2C_ADDR0 (LSB). This
transfer should be MSB first.
Send the write indicator bit (0).
Wait for the AD8197 to acknowledge the request.
Send the register address (eight bits) from which data is to
be read. This transfer should be MSB first.
Wait for the AD8197 to acknowledge the request.
Send a repeated start condition (Sr) by holding the
I2C_SCL line high and pulling the I2C_SDA line low.
The upper four bits of the AD8197 part address are the
static value [1001] and the three LSBs are set by the Input
Pin I2C_ADDR2, I2C_ADDR1 and Input Pin I2C_ADDR0
(LSB). This transfer should be MSB first.
the register indicated by the address set in Step 5. This data
is sent MSB first.
13a. S
EXAMPLE
Resend the AD8197 part address (seven bits) from Step 2.
Send the read indicator bit (1).
I2C_SDA
I2C_SDA
I2C_SCL
2
C master, unless otherwise specified. For a diagram of
line high, pull the SDA line high) and release control
of the bus to end the transaction (shown in Figure 30).
end a st
START
1
op condition (while holding the I2C_SCL
FIXED PART
2
ADDR
ADDR
R/W
3
ACK
4
2
5
C master (such
REGISTER ADDR
Figure 30. I
PrA | Page 17 of 32
2
C Read Diagram
ACK
6
7
SR
SWITCH
There is a delay between when a user writes to the configura-
tion registers of the AD8197 and when tha
physical effect. This update delay occurs regardless of whether
the user programs the AD8197 via the serial or the parallel
control interface. When using the serial control interface, the
update delay begins at the falling edge of I2C_SCL for the last
data bit transferred, as shown in Figure 29. When using the
parallel control interface, the update delay begins at the
transition edge of the relevant parallel interface pin. This updat
delay is register specific and the times are specified in Table 1
During a delay window, new values can be written to the
configuration registers but the AD8197 does not physically
update until the end of that register’s delay window. Writin
new values during the delay window does not reset the wind
new values supersede the previously written values. At the en
of the delay window, the AD8197 physically assumes the state
indicated by the last set of values written to the configuration
registers. If the configuration registers are written after the delay
window ends, the AD8197 immediately updates and a new
delay window begins.
FIXED PART
13b.
13c.
13d.
8
ADDR
Send a repeated start condition (while holding the
I2C_SCL lin
co
Write Procedure section) to perform a write.
Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 of this procedure to perform a
read from another address.
Send a repeated start condition (while holding the
I2C_SCL line high, pull the I
co
read from the same address.
ING/UPDATE DELAY
ntinue
ntinue
ADDR
with Step 2 of the write procedure (prev
with Step 8 of this procedure to perform a
e high, pull the I2C_SDA line low) and
R/W
9 10 11
ACK
DATA
2C_SDA line low) and
t state change takes
ACK
12
AD8197
STOP
13
g
ious
ow;
.
d
e