ADP161 Analog Devices, Inc., ADP161 Datasheet - Page 5

• Manufacturer Part Number: ADP161
• Description: Ultralow Quiescent Current, 150 Ma, Cmos Linear Regulator Adp160/adp161
• Manufacturer: Analog Devices, Inc.

ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VOUT to GND
EN to GND
Storage Temperature Range
Operating Junction Temperature Range
Operating Ambient Temperature Range
Soldering Conditions
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings only apply individually; they do not
apply in combination. The ADP160/ADP161 can be damaged
when the junction temperature limits are exceeded. Monitoring
ambient temperature does not guarantee that T
specified temperature limits. In applications with high power
dissipation and poor thermal resistance, the maximum ambient
temperature may have to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (T
the device is dependent on the ambient temperature (T
power dissipation of the device (P
thermal resistance of the package (θ
Maximum junction temperature (T
temperature (T
T
J
= T
A
+ (P
A
) and power dissipation (P
D
× θ
JA
)
J
) is calculated from the ambient
D
), and the junction to ambient
JA
).
D
) using the formula
Rating
−0.3 V to +6.5 V
−0.3 V to VIN
−0.3 V to VIN
−65°C to +150°C
−40°C to +125°C
−40°C to +125°C
JEDEC J-STD-020
J
is within the
A
), the
J
) of
Rev. 0 | Page 5 of 20
Junction-to-ambient thermal resistance (θ
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on the
application and board layout. In applications where high maximum
power dissipation exists, close attention to thermal board design
is required. The value of θ
layout, and environmental conditions. The specified values of
θ
to JESD 51-7 and JESD 51-9 for detailed information on the
board construction. For additional information, see
Note
Ψ
with units of °C/W. Ψ
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Electronic Package Thermal Information,
states that thermal characterization parameters are not the same
as thermal resistances. Ψ
through multiple thermal paths rather than a single path as in
thermal resistance, θ
convection from the top of the package as well as radiation from
the package, factors that make Ψ
applications. Maximum junction temperature (T
from the board temperature (T
using the formula
Refer to JESD51-8 and JESD51-12 for more detailed information
about Ψ
THERMAL RESISTANCE
θ
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
5-Lead TSOT
4-Ball, 0.4 mm Pitch WLCSP
ESD CAUTION
JA
JA
JB
are based on a 4-layer, 4 inches × 3 inches, circuit board. Refer
and Ψ
is the junction to board thermal characterization parameter
T
AN-617, MicroCSP™ Wafer Level Chip Scale Package.
J
= T
JB
.
JB
B
are specified for the worst-case conditions, that is, a
+ (P
D
× Ψ
JB
JB
. Therefore, Ψ
JB
)
of the package is based on modeling and
JB
JA
measures the component power flowing
may vary, depending on PCB material,
θ
170
260
B
JA
) and power dissipation (P
JB
more useful in real-world
JB
thermal paths include
ADP160/ADP161
Ψ
43
58
JA
) of the package is
JB
J
) is calculated
Application
Unit
°C/W
°C/W
D
)