LM3S1435 Luminary Micro, Inc, LM3S1435 Datasheet - Page 17
LM3S1435
Manufacturer Part Number
LM3S1435
Description
Lm3s1435 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1435.pdf
(521 pages)
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Synchronous Serial Interface (SSI) ............................................................................................ 337
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Inter-Integrated Circuit (I
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Analog Comparator ..................................................................................................................... 409
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
July 25, 2008
SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 349
SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 351
SSI Data (SSIDR), offset 0x008 ...................................................................................... 353
SSI Status (SSISR), offset 0x00C ................................................................................... 354
SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 356
SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 357
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 359
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 360
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 361
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 362
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 363
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 364
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 365
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 366
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 367
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 368
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 369
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 370
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 371
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 372
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 373
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 413
Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 414
Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 415
Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 416
Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 417
Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 418
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 388
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 389
C Master Data (I2CMDR), offset 0x008 ......................................................................... 393
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 394
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 395
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 396
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 397
C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 398
C Master Configuration (I2CMCR), offset 0x020 ............................................................ 399
C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 401
C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 402
C Slave Data (I2CSDR), offset 0x008 ........................................................................... 404
C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 405
C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 406
C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 407
C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 408
2
C) Interface ........................................................................................ 374
Preliminary
LM3S1435 Microcontroller
17
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