LM3S6952 Luminary Micro, Inc, LM3S6952 Datasheet - Page 10

• Manufacturer Part Number: LM3S6952
• Description: Lm3s6952 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Figure 15-3.
Figure 15-4.
Figure 15-5.
Figure 15-6.
Figure 15-7.
Figure 15-8.
Figure 15-9.
Figure 15-10. Master Burst RECEIVE .................................................................................................. 390
Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 391
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 392
Figure 15-13. Slave Command Sequence ............................................................................................ 393
Figure 16-1.
Figure 16-2.
Figure 16-3.
Figure 17-1.
Figure 17-2.
Figure 17-3.
Figure 18-1.
Figure 18-2.
Figure 18-3.
Figure 18-4.
Figure 18-5.
Figure 18-6.
Figure 19-1.
Figure 19-2.
Figure 20-1.
Figure 20-2.
Figure 23-1.
Figure 23-2.
Figure 23-3.
Figure 23-4.
Figure 23-5.
Figure 23-6.
Figure 23-7.
Figure 23-8.
Figure 23-9.
Figure 23-10. JTAG TRST Timing ........................................................................................................ 569
Figure 23-11. External Reset Timing (RST) .......................................................................................... 570
Figure 23-12. Power-On Reset Timing ................................................................................................. 571
Figure 23-13. Brown-Out Reset Timing ................................................................................................ 571
Figure 23-14. Software Reset Timing ................................................................................................... 571
Figure 23-15. Watchdog Reset Timing ................................................................................................. 571
Figure 24-1.
Figure 24-2.
10
START and STOP Conditions ......................................................................................... 383
Complete Data Transfer with a 7-Bit Address ................................................................... 384
R/S Bit in First Byte ........................................................................................................ 384
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 387
Master Single RECEIVE ................................................................................................. 388
Master Burst SEND ....................................................................................................... 389
Ethernet Controller Block Diagram .................................................................................. 418
Ethernet Controller ......................................................................................................... 418
Ethernet Frame ............................................................................................................. 420
Analog Comparator Module Block Diagram ..................................................................... 462
Structure of Comparator Unit .......................................................................................... 463
Comparator Internal Reference Structure ........................................................................ 464
PWM Unit Diagram ........................................................................................................ 474
PWM Module Block Diagram .......................................................................................... 475
PWM Count-Down Mode ................................................................................................ 476
PWM Count-Up/Down Mode .......................................................................................... 476
PWM Generation Example In Count-Up/Down Mode ....................................................... 477
PWM Dead-Band Generator ........................................................................................... 477
QEI Block Diagram ........................................................................................................ 510
Quadrature Encoder and Velocity Predivider Operation .................................................... 512
100-Pin LQFP Package Pin Diagram .............................................................................. 527
108-Ball BGA Package Pin Diagram (Top View) ............................................................... 528
Load Conditions ............................................................................................................ 560
I
External XTLP Oscillator Characteristics ......................................................................... 565
Hibernation Module Timing ............................................................................................. 566
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 567
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 567
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 568
JTAG Test Clock Input Timing ......................................................................................... 569
JTAG Test Access Port (TAP) Timing .............................................................................. 569
100-Pin LQFP Package .................................................................................................. 572
108-Ball BGA Package .................................................................................................. 574
2
C Timing ..................................................................................................................... 563
Preliminary
2
C Bus ............................................................... 384
July 25, 2008