LM3532TMX-40ANOPB National Semiconductor Corporation, LM3532TMX-40ANOPB Datasheet - Page 25

• Manufacturer Part Number: LM3532TMX-40ANOPB
• Description: High Efficiency White Led Driver With Programmable Ambient Light Sensing Capability And I2c-compatible Interface
• Manufacturer: National Semiconductor Corporation

I
START AND STOP CONDITION
The LM3532 is controlled via an I
START and STOP conditions classify the beginning and the
end of the I
transitioning from HIGH-to-LOW while SCL is HIGH. A STOP
condition is defined as SDA transitioning from LOW-to-HIGH
while SCL is HIGH. The I
I
The 7-bit chip address for the LM3532 is (0x38) . After the
START condition, the I
followed by an eighth bit (LSB) read or write (R/W). R/W = 0
Transferring Data
Every byte on the SDA line must be eight bits long, with the
most significant bit (MSB) transferred first. Each byte of data
must be followed by an acknowledge bit (ACK). The acknowl-
edge related clock pulse (9th clock pulse) is generated by the
2
2
C-Compatible Address
C-Compatible Interface
2
C session. A START condition is defined as SDA
2
C master sends the 7-bit chip address
2
C master always generates the
2
C-compatible interface.
FIGURE 15. I
FIGURE 14. Start and Stop Sequences
2
C-Compatible Chip Address (0x38)
25
START and STOP conditions. The I
after a START condition and free after a STOP condition.
During data transmission, the I
peated START conditions. A START and a repeated START
conditions are equivalent function-wise. The data on SDA
must be stable during the HIGH period of the clock signal
(SCL). In other words, the state of SDA can only be changed
when SCL is LOW.
indicates a WRITE and R/W = 1 indicates a READ. The sec-
ond byte following the chip address selects the register ad-
dress to which the data will be written. The third byte contains
the data for the selected register.
master. The master then releases SDA (HIGH) during the 9th
clock pulse. The LM3532 pulls down SDA during the 9th clock
pulse, signifying an acknowledge. An acknowledge is gener-
ated after each byte has been received.
2
30115403
C master can generate re-
2
C bus is considered busy
30115438
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