LM3S1937-IBZ50 Luminary Micro, Inc, LM3S1937-IBZ50 Datasheet - Page 10

• Manufacturer Part Number: LM3S1937-IBZ50
• Description: Lm3s1937 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Figure 15-3.
Figure 15-4.
Figure 15-5.
Figure 15-6.
Figure 15-7.
Figure 15-8.
Figure 15-9.
Figure 15-10. Master Burst RECEIVE .................................................................................................. 383
Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 384
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 385
Figure 15-13. Slave Command Sequence ............................................................................................ 386
Figure 16-1.
Figure 16-2.
Figure 16-3.
Figure 17-1.
Figure 17-2.
Figure 17-3.
Figure 17-4.
Figure 17-5.
Figure 17-6.
Figure 18-1.
Figure 18-2.
Figure 21-1.
Figure 21-2.
Figure 21-3.
Figure 21-4.
Figure 21-5.
Figure 21-6.
Figure 21-7.
Figure 21-8.
Figure 21-9.
Figure 21-10. External Reset Timing (RST) .......................................................................................... 495
Figure 21-11. Power-On Reset Timing ................................................................................................. 496
Figure 21-12. Brown-Out Reset Timing ................................................................................................ 496
Figure 21-13. Software Reset Timing ................................................................................................... 496
Figure 21-14. Watchdog Reset Timing ................................................................................................. 496
Figure 22-1.
Figure 22-2.
10
START and STOP Conditions ......................................................................................... 376
Complete Data Transfer with a 7-Bit Address ................................................................... 377
R/S Bit in First Byte ........................................................................................................ 377
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 380
Master Single RECEIVE ................................................................................................. 381
Master Burst SEND ....................................................................................................... 382
Analog Comparator Module Block Diagram ..................................................................... 410
Structure of Comparator Unit .......................................................................................... 411
Comparator Internal Reference Structure ........................................................................ 412
PWM Unit Diagram ........................................................................................................ 421
PWM Module Block Diagram .......................................................................................... 422
PWM Count-Down Mode ................................................................................................ 423
PWM Count-Up/Down Mode .......................................................................................... 423
PWM Generation Example In Count-Up/Down Mode ....................................................... 424
PWM Dead-Band Generator ........................................................................................... 424
100-Pin LQFP Package Pin Diagram .............................................................................. 457
108-Ball BGA Package Pin Diagram (Top View) ............................................................... 458
Load Conditions ............................................................................................................ 488
I
Hibernation Module Timing ............................................................................................. 491
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 492
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 492
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 493
JTAG Test Clock Input Timing ......................................................................................... 494
JTAG Test Access Port (TAP) Timing .............................................................................. 494
JTAG TRST Timing ........................................................................................................ 494
100-Pin LQFP Package .................................................................................................. 497
108-Ball BGA Package .................................................................................................. 499
2
C Timing ..................................................................................................................... 491
Preliminary
2
C Bus ............................................................... 377
July 25, 2008