LM3S1937-IBZ50 Luminary Micro, Inc, LM3S1937-IBZ50 Datasheet - Page 18

• Manufacturer Part Number: LM3S1937-IBZ50
• Description: Lm3s1937 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Pulse Width Modulator (PWM) .................................................................................................... 421
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
18
PWM Master Control (PWMCTL), offset 0x000 ................................................................ 429
PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 430
PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 431
PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 432
PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 433
PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 434
PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 435
PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 436
PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 437
PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 438
PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 438
PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 438
PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 440
PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 440
PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................... 440
PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 442
PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 442
PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 442
PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 443
PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 443
PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ........................................... 443
PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 444
PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 444
PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 444
PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 445
PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 445
PWM2 Counter (PWM2COUNT), offset 0x0D4 ............................................................... 445
PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 446
PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 446
PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................. 446
PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 447
PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 447
PWM2 Compare B (PWM2CMPB), offset 0x0DC ............................................................ 447
PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 448
PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 448
PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ................................................ 448
PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 451
PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 451
PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ................................................ 451
PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 454
PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 454
PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ................................................ 454
PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 455
PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 455
PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................. 455
PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 456
PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 456
Preliminary
July 25, 2008