HMP8170CN Intersil Corporation, HMP8170CN Datasheet - Page 24

• Manufacturer Part Number: HMP8170CN
• Description: NTSC/PAL Video Encoder
• Manufacturer: Intersil Corporation

Pin Descriptions
NTSC/PAL 1
NTSC/PAL 2
FS_ADJUST
COMP 1
COMP 2
RESET
NAME
VREF
CLK2
GND
CLK
SCL
SDA
VAA
PIN
SA
Y
C
NUMBER
PIN
39
41
18
19
20
25
11
15
61
62
64
63
3
7
(Continued)
24
OUTPUT
HMP8170, HMP8171, HMP8172, HMP8173
INPUT/
I/O
I/O
I/O
O
O
O
O
I
I
I
I
1x pixel clock input/output. As an input, this clock must be free-running and synchronous to
the clock signal on the CLK2 pin. As an output, this pin may drive a maximum of one LS TTL
load. CLK is generated by dividing CLK2 by two or four, depending on the mode. If not
driven, the circuit for this pin should include a 4-12k pull up resistor connected to VAA.
2x pixel clock input. This clock must be a continuous, free-running clock.
I
connected to VAA.
I
I
connected to VAA.
Reset control input. A logical zero for a minimum of four CLK cycles resets the device.
RESET must be a logical one for normal operation.
Luminance analog current output. This output contains luminance video, sync, blanking, and
information. In analog YUV or RGB output mode, an alternate signal is generated (see Table
12). It is capable of driving a 37.5 load. If not used, it should be connected to GND.
Chrominance analog current output. This output contains chrominance video, and blanking
information. In analog YUV or RGB output mode, an alternate signal is generated (see Table
12). It is capable of driving a 37.5 load. If not used, it should be connected to GND.
Composite video analog current output. This output contains composite video, sync,
blanking, and information. In analog YUV or RGB output mode, an alternate signal is
generated (see Table 12). It is capable of driving a 37.5 load. If not used, it should be
connected to GND.
Composite video analog current output. This output contains composite video, sync,
blanking, and information. In analog YUV or RGB output mode, an alternate signal is
generated (see Table 12). It is capable of driving a 37.5 load. If not used, it should be
connected to GND.
Voltage reference. An optional external 1.235V reference may be used to drive this pin. If
left floating, the internal voltage reference is used.
Full scale adjust control. A resistor (RSET) connected between this pin and GND sets the
full-scale output current of each of the DACs.
Compensation pin. A 0.1 F ceramic chip capacitor should be connected between this pin
and VAA, as close to the device as possible.
Compensation pin. A 0.1 F ceramic chip capacitor should be connected between this pin
and VAA as close to the device as possible.
+5V power. A 0.1 F ceramic capacitor, in parallel with a 0.01 F chip capacitor, should be
used between each group of VAA pins and GND. These should be as close to the device as
possible.
Ground
2
2
2
C interface clock input. The circuit for this pin should include a 4-6k pull-up resistor
C interface address select input.
C interface data input/output. The circuit for this pin should include a 4-6k pull-up resistor
DESCRIPTION