CLA200 Zarlink Semiconductor, CLA200 Datasheet - Page 4

• Manufacturer Part Number: CLA200
• Description: CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

CLA200 Series
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Memory Paracells
The standard CLA200 Series gate array architecture has been
designed to allow for the implementation of memory within the
design. A memory compiler (PMG) is available which allows
designers to specify the number of bits and words required.
The PMG can automatically create design views for all of the
supported CAE tools.
Features of the Gate Array memory include :
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Typical Memory speeds for a range of Gate Array RAMs
operating at 3.3V , 25ºC are summarised in the table 1 below.
Parameter
Size
No. Words
No. Bits
Read Access
Write Cycle
Cycle Power
Single and Dual Port memories
Dual port supports: one read and one write port
RAM sizes from 16 to 16k bits
Word length from 2 to 64 bits in steps of 1
Address range from 8 to 256 words in steps of 2
Zero static DC power consumption (only intrinsic leakage)
Separate input and output data busses
0.37
1.2
6.2
16
8
2
0.25
512
2.1
6.5
Table. 1
64
8
512
256
8.5
6.5
3.0
2
Advance Information
16K
256
9.4
6.9
5.8
64
mW/MHz
Words
Units
Bits
Bits
ns
ns
CLOCK AND POWER DISTRIBUTION
It is known that large, complex designs working at high speed
are vulnerable to problems associated with poor clock and
power distribution. Zarlink Semiconductor has published
design notes that describe approaches to clock and power
distribution.
Clock Distribution
The CLA200 Series supports a number of Clock distribution
methodologies which may be implemented depending on the
particular design and the CAD tools being used by the
designer. For small designs with a light clock load, a single
large buffer may be sufficient. For large designs, with large
clock loads, a clock grid or clock tree is recommended to avoid
clock skew and metal electromigration in the clock network.
Clock trees can either be synthesized or manually specified as
a clock hierarchy by the designer.
The CLA200 Series clock grid methodology uses up to three
stages of buffers, where each stage drives a grid which feeds
the next stage cells (figure 1).
The final stage grid is a starting point for routing to the actual
clocked inputs. Figure 2 illustrates the layout of each buffer
stage, which is done automatically at layout.
Power Distribution
CLA200 can be used from 1.8 to 3.3V, giving great flexibility
of supply voltage. Core supply can be chosen from a nominal
2V or 3.3V, with mixed voltage I/O available if the core supply
is 2V. I/O cells are available as either CMOS or TTL
compatible for all supply configurations.
The CLA200 Series utilises a grid methodology for power
distribution. This grid, which is automatically constructed
during layout, uses metal layers one and three for horizontal
power rails and metal layer two for vertical connections. Metal
layer four is also available for vertical connections, which may
be useful on some larger arrays. Methods of implementation
are available for use with flat layout, manual methods, or
hierarchical layout.