CLA90000 Zarlink Semiconductor, CLA90000 Datasheet - Page 4

• Manufacturer Part Number: CLA90000
• Description: High Density CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

CLOCK AND POWER DISTRIBUTION
I Low clock skew distribution strategies
I Power grid to minimize voltage drop
It is known in the industry that large, complex designs
working at high speed are vulnerable to problems associ-
ated with poor clock and power distribution. The following
sections indicate how the Zarlink design and layout meth-
odology avoids these problems.
Clock Distribution
Zarlink has experience with a variety of layout methods to
prevent clock skew problems. The preferred method is to
use built-in clock grid generation and drive the clock grids
with buffers distributed throughout the chip, which limits
skew to below 70ps and provides a reliable solution to
clock distribution suitable for most designs. For all clock
strategies, post-layout clock delays are extracted and fed
back for resimulation. An example of one clock distribution
method is illustrated below.
Figure 1 Example Clock Distribution
4
Pad Ring
Subcircuit
Local
clock grid
Global
clocks
Power Distribution and Estimation
The Zarlink layout methodology constructs grids for all
array size options, including optimized arrays. This grid
can use metal layers one and two for horizontal and verti-
cal grids, and metal layer three may also be used on some
larger arrays. Methods of implementation are available for
use with flat layout, manual methods, or hierarchy. A sim-
plified grid arrangement is shown below. In addition the
CLA90000 series of arrays is supported by EPIC Power-
Mill  power estimation software (check availability)..
MANUFACTURING
I Class 10 clean room
I Advanced equipment including mini-environments and
I Statistical process control (SPC) monitoring of all
I Vibration-free for reliable manufacture
I Two silicon sources
The CLA90000 product is manufactured near Plymouth,
England in a purpose-built vibration-free factory for sub-
micron process geometries. The factory uses the latest
automated equipment for 8-inch wafers in class 10 clean
room conditions with SMIF boxes for semi-automatic
handling. Computer aided manufacture ensures production
efficiency and the lowest possible defect level. In addition
to the world class wafer fabrication facility, the probe and
final test areas are equipped with the latest analog and
digital testers. Zarlink Semiconductor is committed to
continuous investment to provide state-of-the-art CMOS
ASICs. A qualified second source for this silicon process is
available.
Optional horizontal metal-3 grid
SMIF box transportation between processes
stages
Figure 2 Power Grid
Vertical metal-2 gr
Pads