CLA90000 Zarlink Semiconductor, CLA90000 Datasheet - Page 7

• Manufacturer Part Number: CLA90000
• Description: High Density CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

ADVANCED DELAY MODELLING
I Edge speed modelling
I Pin to pin timings
I Nonlinear delay modelling
I Accurate delay derating
Pin to Pin Delays
Delay models use times between individual input and out-
put pins for both rising and falling delays, as illustrated
below.
The use of individual pin to pin delays, e.g. A to F and B to
F, improves simulation accuracy as there can be consider-
able variation in delay between different input pins. For
complex gates (e.g. AND-NOR gates or adders) the varia-
tion is up to 40%. For simple NAND and NOR logic gates
the typical variation is 20%.
Nonlinear Curve Fitting
For fast input edges (0.5ns) delay time increases linearly
with the output load, whereas for high output loads delay
increases linearly with edge speed. Delays for slow input
edges and light input loads do not follow the linear model,
so a simple linear model cannot represent delays accu-
rately. A more complex formula, which includes interaction
between edge and load factors, is used to model delays for
CLA90000.
A
B
C
Figure 4 Delay Paths
F
THERMAL MANAGEMENT
I Lower power CMOS for improved thermal management
I 0.5 µ W/MHz/gate (3V supply 2-input NAND with 2
I Software constructed power grids for efficient power
I Copper lead frame QFPs for lower thermal resistance
I High pinout power packages available
The increase in speed and density available through
advanced CMOS processes results in a corresponding
increase in power dissipation. Semicustom designers now
have the ability to design circuits in excess of half a million
usable gates, and chip power consumption is an important
issue.
To meet the requirements of high speed, high gate count
designs, Zarlink CLA90000 arrays offer low power factors
and a selection of power packages for improved thermal
management.
QUALITY AND RELIABILITY
I Statistical process control used in manufacture
I Regular sample screening and reliability testing
I Screening to MIL and other recognized standards is
At Zarlink, quality and reliability are built into the product
by statistical control of all processing operations and by
minimizing random uncontrolled effects in all manufactur-
ing operations. Process management involves full docu-
mentation of procedures with recording of batch by batch
data using computerized WIP tracking systems.
A common information management system is used to
monitor the manufacturing of Zarlink CMOS processes
and operations. All products benefit from the use of this
integrated monitoring system resulting in the highest qual-
ity standards for all technologies.
Further information and reliability results are contained in
the Quality MOS Brochure, available from Zarlink Sales
Offices.
loads)
distribution
available
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