MT9160AS Mitel Semiconductor, MT9160AS Datasheet - Page 4

• Manufacturer Part Number: MT9160AS
• Description: ISO2-CMOS 5 Volt Multi-Featured Codec (MFC)
• Manufacturer: Mitel Semiconductor

MT9160
Overview
The
complete
conversion of audio signals (Filter/Codec) and an
analog interface to a standard handset transmitter
and receiver (Transducer Interface). The receiver
amplifier is capable of driving a 300 ohm load.
Each of the programmable parameters within the
functional blocks is accessed through a serial
microcontroller port compatible with Intel MCS-51
Motorola
Microwire
include: gain control, power down, mute, B-Channel
select (ST-BUS mode), C&D channel control/access,
law control, digital interface programming and
loopback. Optionally the device may be used in a
controllerless mode utilizing the power-on default
settings.
Functional Description
Filter/Codec
The Filter/Codec block implements conversion of the
analog 0-3.3 kHz speech signals to/from the digital
domain compatible with 64 kb/s PCM B-Channels.
Selection of companding curves and digital code
assignment are programmable. These are CCITT
G.711 A-law or -Law, with true-sign/ Alternate Digit
Inversion or true-sign/Inverted Magnitude coding,
respectively. Optionally, sign- magnitude coding may
also be selected for proprietary applications.
The Filter/Codec block also implements transmit and
receive audio path gains in the analog domain. A
programmable gain, voice side-tone path is also
included to provide proportional transmit speech
feedback to the handset receiver. This side tone path
feature is disabled by default. Figure 3 depicts the
nominal half-channel and side-tone gains for the
MT9160.
In the event of PWRST, the MT9160 defaults such
that the side-tone path is off, all programmable gains
are set to 0dB and CCITT -Law is selected. Further,
the digital port is set to SSI mode operation at 2048
kb/s and the FDI and driver sections are powered up.
(See Microport section.)
The internal architecture is fully differential to provide
the best possible noise rejection as well as to allow a
wide dynamic range from a single 5 volt supply
Intel® and MCS-51® are registered trademarks of Intel Corporation
Motorola® and SPI® are registered trademarks of Motorola Corporation
National® and Microwire® are trademarks of National Semiconductor Corporation
7-80
5V
®
Multi-featured
SPI
Analog/Digital
specifications.
®
and
National
Codec
and
These
(MFC)
Semiconductor
Digital/Analog
parameters
features
®
,
design.
continued into the Transducer Interface section to
provide full chip realization of these capabilities for
the handset functions.
A reference voltage (V
requirements of the Codec section, and a bias
voltage (V
sections, are both generated on-chip. V
brought to an external pin so that it may be used for
biasing external gain setting amplifiers. A 0.1 F
capacitor must be connected from V
ground at all times. Likewise, although V
be used internally, a 0.1 F capacitor from the V
pin to ground is required at all times. The analog
ground reference point for these two capacitors must
be physically the same point. To facilitate this the
V
The transmit filter is designed to meet CCITT G.714
specifications. The nominal gain for this filter is 0 dB
(gain control = 0 dB). Gain control allows the output
signal to be increased up to 7 dB. An anti-aliasing
filter is included. This is a second order lowpass
implementation with a corner frequency at 25 kHz.
The receive filter is designed to meet CCITT G.714
specifications. The nominal gain for this filter is 0 dB
(gain control = 0dB). Gain control allows the output
signal to be attenuated up to 7 dB. Filter response is
peaked to compensate for the sinx/x attenuation
caused by the 8 kHz sampling rate.
Side-tone is derived from the input of the Tx filter and
is not subject to the gain control of the Tx filter
section. Side-tone is summed into the receive
handset transducer driver path after the Rx filter gain
control section so that Rx gain adjustment will not
affect side-tone levels. The side-tone path may be
enabled/disabled with the gain control bits located in
Gain Control Register 2 (address 01h).
Transmit and receive filter gains are controlled by the
TxFG
respectively. These are located in Gain Control
Register 1 (address 00h). Transmit filter gain is
adjustable from 0 dB to +7 dB and receive filter gain
from 0dB to -7 dB, both in 1 dB increments.
Side-tone filter gain is controlled by the STG
control bits located in Gain Control Register 2
(address 01h). Side-tone gain is adjustable from
-9.96 dB to +9.96 dB in 3.32 dB increments.
Ref
and V
0
-TxFG
This
Bias
Bias
2
), for biasing the internal analog
pins are situated on adjacent pins.
and
fully
Preliminary Information
RxFG
differential
Ref
0
), for the conversion
-RxFG
2
architecture
Bias
control
Ref
Bias
to analog
may only
0
is also
-STG
bits,
Ref
is
2