MT8986 Mitel Semiconductor, MT8986 Datasheet
MT8986
Available stocks
Related parts for MT8986
MT8986 Summary of contents
Page 1
... In addition, the MT8986 can be used for switching of 32 kb/s channels in ADPCM applications. The MT8986 is ideal for medium size mixed voice and data switching/processing applications. ...
Page 2
... MT8986 STi3 8 STi4 9 STi5 10 STi6/A6 11 STi7/A7 12 VDD CLK 15 STi8/A0 16 STi9/A1 STi10/ PIN PLCC Pin Description Pin # Name DIP PLCC QFP DTA Data Acknowledgement (Open Drain Output). This active low output indicates that a data bus transfer is complete ...
Page 3
... MHz. 13-15 15-17 9-11 A0-2/ Address 0-2 / Input Streams 8-10 (Input). When non-multiplexed CPU bus is STi8-10 selected, these lines provide the A0-A2 address lines to MT8986 internal registers. When 16x8 switching configuration is selected (in 44 pin only), then these pins are ST-BUS serial inputs receiving data at 2.048 Mb/s. 16-18 19-21 13-15 A3-5/ Address 3-5 / Input Streams 11-13 (Input) ...
Page 4
... The falling edge of this signal is used to sample the address into the address latch circuit. In case of non-multiplexed bus, this input is not required and should be left open CPU Interface Mode (Input). If HIGH, this input configures MT8986 in multiplexed microprocessor bus mode. If this input pin is not connected or grounded, the MT8986 assumes non-multiplexed CPU interface STi15/ ST-BUS Input 15 / ST-BUS Output 9 (Input/three-state output) ...
Page 5
... Non-Multiplexed or Multiplexed. These interfaces provide compatibility with Intel/ National multiplexed and Motorola Multiplexed/Non- Multiplexed buses pin, the MT8986 provides switching configuration to form a 512 x 256 channel blocking matrix. Also, a flexible Stream Pair Selection operation allows the software selection of which pair of input and output streams can be connected to an internal 128 x 128 matrix ...
Page 6
... CLKM bit has no effect. In applications with serial links at 2.048 Mb/s (see Figures 16 to 19), the input 8 kHz frame pulse can be in either ST-BUS or GCI format. The MT8986 device automatically detects the presence of an input frame pulse and identifies what type of backplane is present on the serial interface ...
Page 7
... Kb/s channels each. For this operation, a 4.096 MHz interface clock equal to the bit rate should be provided to MT8986. Only variable throughput delay mode is provided. In case switching configuration, a 256 x 256 channel non-blocking switch is available with serial streams carrying 64, 64 Kb/s channels each. In this configuration, the interface clock is 4 ...
Page 8
... This may result in the system frame synchronization pulse to be active at the MT8986 FR input before the first bit of the frame is received at the serial inputs. When the input frame offset is enabled, an "internal delay" four clock periods is added to the actual data input sampling, providing the MT8986 serial timing unit a new input frame reference ...
Page 9
... Except for 2 Mb Mb/s and 2 Mb Mb/s rate conversion operations, the throughput delay in the MT8986 may vary according to the output stream used for switching. Table 3b explains the worst case conditions for the throughput delay when different I/O data rate switching configurations are used. ...
Page 10
... Software Control The address bus on the microprocessor interface selects the internal registers and memories of the MT8986. If the A5 address input is LOW, then the MT8986 Internal Control, Interface Mode, Stream Pair Selection and Frame Input Offset registers are addressed by the bits according to Table 5. ...
Page 11
... Connect Memory LOW (CML) are output on the ST-BUS output streams once every frame unless the ODE input pin is LOW bit is HIGH, then the MT8986 behaves as if bits 2 (Message Channel) and 0 (Output Enable) of every A7 A6 ...
Page 12
... On initialization or power up, the contents of the Connection Memory High can be in any state. This is a potentially hazardous condition when multiple MT8986 ST-BUS outputs are tied together to form matrices, as these outputs may conflict. The ODE pin should be held low on power up to keep all outputs in the high impedance condition ...
Page 13
... DMO bit of the Interface Mode Selection register. Tables 6 and 7 show the utilization of these bits according to the device’s main operation. Figure 3 - Control Register Description Control Register - Read/Write STA3 MS1 MS0 STA2 DESCRIPTION MT8986 1 0 STA1 STA0 2-75 ...
Page 14
... MT8986 Identical # of Input x select subsections I/O Output Rate Streams 2 Mb/s 8x8 STA2, STA1, STA0 2 Mb/s * 4x4 * STA1, STA0 2 Mb/s * 16x8 * STA3, STA2, STA1, STA0 4 Mb/s 4x4 STA1, STA0 4 Mb/s 8x4 STA2, STA1, STA0 8 Mb/s 2x2 STA0 Nibble Switch 8x4 STA2, STA1, STA0 (2 Mb/s) Table 6. Use of STA Bits for Identical I/O Data Rate Operation * - only in the 44 pin packages ...
Page 15
... Non-Blocking switch configuration with a 256 x 256 channel capacity. 6-5 IDR1-0 Input Data Rate Selection. These two bits select three different data rates for the inputs of the MT8986. In the case of identical I/O rates (DMO bit = 0), these bits also determine the serial output data rate. IDR1 4-3 ODR1-0 Output Data Rate Selection ...
Page 16
... MT8986 Data Rate Selected DMO Bit at IDR bits (Mb/s) 2.048 LOW Identical I/O Rates 4.096 8.192 HIGH Input/Output Rate selected in Different I/O IDR/ODR bits Rates Table 8. Switching Configurations for Identical I/O Rates ** 44 pin packages only 2-78 SCB1 SCB0 inputs x 8 outputs - Non Blocking inputs x 8 outputs - Blocking** ...
Page 17
... Output Enable. This bit enables the output drivers on a per-channel basis. This allows individual channels on individual streams to be made high-impedance, allowing switch matrices to be constructed. A HIGH enables the driver and a LOW disables it. Figure 5 - Connection Memory High (CMH) Bits x=Don’t care V/C SAB3 CAB6 CAB5 MC (CM high bits) DESCRIPTION MT8986 1 0 CSTo OE 2-79 ...
Page 18
... MT8986 Connection Memory Low - Read/Write 7 SAB2 BIT NAME 7-5 SAB2-0* Source Stream Address bits. These three bits are used together with SAB3 in CMH to select different source streams for the connection. Depending on the switching configuration and the data rate selected in the application all 4 SAB bits can be used ...
Page 19
... Reserved Reserved Reserved MT8986 1 0 SPB1 SPB0 STi2 / STo2 STi3 / STo3 STi4 / STo4 STi5 / STo5 STi6 / STo6 STi7 / STo7 STi8 / STo8 STi9 / STo9 STi2 / STo2 STi3 / STo3 STi4 / STo4 STi5 / STo5 STi6 / STo6 STi7 / STo7 ...
Page 20
... MT8986 Applications Switch Matrix Architectures The MT8986 is an ideal device for designs of medium size switch matrix. For applications where voice and grouped data channels are transported within the same frame, the voice samples have to be time interchanged with a minimum delay while maintaining the integrity of grouped data ...
Page 21
... The external logic described in Figure block diagram of a logical connection between MT8986 and 8051. Its main function is to store the 8051 data during a write and the MT8986 data during a read. For a write, MT8986 address is latched by the internal address latch on the falling edge of the ALE input ...
Page 22
... AD6 AD7 ALE RD WR Figure 14 - Interfacing the MT8986 to the 8051 Microcontroller goes low). Latch U4 stores the MT8986 output data during a read cycle whenever DTA goes low. When writing to the MT8986, one write operation is sufficient. However, when reading MT8986, two read operations with the same address are required, with the second being valid ...
Page 23
... 2 0 Figure 15 - Output Test Load MT8986 Min Max Units -0 -0 -0 -65 +150 ° unless otherwise stated. SS Units Test Conditions ° ...
Page 24
... MT8986 AC Electrical Characteristics Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 Frame Pulse width 2 Frame Pulse setup time 3 Frame Pulse hold time 4 STo delay Active to Active 5 STi setup time 6 STi hold time 7 Clock period 8 CK Input Low 9 CK Input High 10 Clock Rise/Fall Time † ...
Page 25
... Note: bit 0 identifies the first bit of the GCI frame WFH t t FRS FRH DAA Figure 17 - GCI Timing (CLKM bit=0) MT8986 Max Units Test Conditions 300 ns 150 ns ns 190 ns 190 ns 100 ns C =150 =– ...
Page 26
... MT8986 AC Electrical Characteristics Characteristics 1 O STo0/9 Delay - Active to High STo0/9 Delay - High Z to Active Output Driver Enable Delay CSTo Output Delay S † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ...
Page 27
... OED with timing corrected to cancel time taken to discharge C L MT8986 Units Test Conditions =150 =150 pF pF ...
Page 28
... STo Bit 0 B0 STi Figure 20 - Serial Interface Timng (CLKM bit=1, DMO bit=0) - 4.096 and 8.192 Mb/s Note: For 8.192 Mb/s clock, only the positive polarity frame pulse is accepted by the MT8986 device. ODE STo0 to STo9 Figure 21 - Output Driver Enable for Streams at 4.096 and 8.192 Mb/s ...
Page 29
... Figure 22 - Rate Conversion Mode (DMO bit Ch. 0 Ch. 0 Bit 6 Bit 5 Ch. 0 Bit Ch. 0 Bit Ch. 0 Ch. 0 Bit 7 Bit 6 MT8986 2.0V 0.8V 2.0V 0. 2.0V High Z 0.8V 2.0V Ch. 0 Ch. 0 Bit 6 Bit 5 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V Ch. 0 Bit 6 0.8V 2.0V Ch. 0 Bit 5 0.8V 2-91 ...
Page 30
... MT8986 CLK (4.096 MHz (positive Ch. 63 STo Bit 0 Ch. 31 STi Bit 0 CLK (4.096 MHz (negative Ch. 63 STo Bit 0 Ch. 31 STi Bit 0 Figure 23 - Rate Conversion Mode (DMO bit= Mb Mb/s 2- Ch. 0 Ch. 0 Ch. 0 Bit 7 ...
Page 31
... Figure 25 - Rate Conversion Mode (DMO bit Ch. 0 Ch. 0 Bit 6 Bit 5 Ch. 0 Bit Ch. 0 Ch. 0 Bit 6 Bit Ch. 0 Bit 7 MT8986 2.0V 0.8V 2.0V 0. 2.0V High Z 0.8V 2.0V Ch. 0 Bit 6 0.8V 2.0V 0.8V 2.0V 0. 2.0V High Z 0. 2.0V Ch. 0 Bit 6 0.8V 2-93 ...
Page 32
... MT8986 AC Electrical Characteristics Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 ALE pulse width 2 Address setup from ALE falling 3 Address hold from ALE falling 4 RD active after ALE falling 5 Data setup from DTA Low on Read 6 CS hold after RD/ pulse width (fast read) ...
Page 33
... AAAA AAAA AAAA AAAA A DATA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A t SWD CSR CSW t DSW t DDR t AKD MT8986 2.0V 0.8V 2.0V 0.8V t CSRW 2.0V 0.8V 2.0V 0.8V t DHR 2.0V 0.8V t DHW t AKH 2.0V 0.8V 2-95 ...
Page 34
... MT8986 AC Electrical Characteristics Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 AS pulse width 2 Address setup from AS falling 3 Address hold from AS falling 4 Data setup from DTA Low on Read 5 CS hold after DS falling 6 CS setup from DS rising 7 Data hold after write ...
Page 35
... AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA t CSS t DDR t AKD MT8986 2.0V 0.8V t RWH AAAA AAAA AAAA A AAAA AAAA AAAA A A AAAA AAAA AAAA 2.0V AAAA AAAA AAAA A AAAA AAAA AAAA A AAAA ...
Page 36
... MT8986 AC Electrical Characteristics Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 CS Setup from DS rising 2 R/W Setup from DS rising 3 Add setup from DS rising 4 CS hold after DS falling 5 R/W hold after DS falling 6 Add hold after DS falling 7 Data setup from DTA Low on Read ...
Page 37
... DS CS R/W A0-A6 D0-D7 READ D0-D7 WRITE DTA Figure 28 - Motorola Non-Multiplexed Bus Timing t CSS t RWS t ADS VALID DATA t t DSW SWD VALID DATA t t DDR DHW t AKD MT8986 2.0V 0.8V t CSH 2.0V 0.8V t RWH 2.0V 0.8V t ADH 2.0V 0.8V 2.0V 0.8V t DHR 2.0V 0.8V t AKH 2.0V 0.8V 2-99 ...
Page 38
... MT8986 NOTES 2-100 ...