CA3194 Intersil, CA3194 Datasheet - Page 3

• Manufacturer Part Number: CA3194
• Description: Single Chip PAL Luminance/Chroma Processor
• Manufacturer: Intersil

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Electrical Specifications
NOTES:
Circuit Description
The chroma signal is externally separated from the video
signal by means of a bandpass or high-pass filter and
applied to pin 4. The burst is separated in the first chroma
stage and applied to the synchronous detector which pro-
vides information to sample-and-hold circuits for APC
(phase-locked loop), ACC (automatic chroma gain control)
and identification and killing. The 4.43MHz crystal oscillator
is phase-locked to the burst and provides 0 degrees and 90
degrees (via an external phase shifter) carriers to the
chroma demodulators. The burst and chroma amplitude at
the output of the first chroma amplifier is kept constant by
the automatic gain control.
The second chroma stage provides saturation control (pin 3)
which tracks the contrast control in the luminance channel.
This stage is also used for color killing.
Saturation Control Range (Terminal 3)
Maximum Chroma Output Voltage (Terminal 2)
OSCILLATOR SECTION
Pull-In Range
Static Phase Error
DEMODULATOR SECTION
R-Y Demodulator Conversion Gain
B-Y Demodulator Conversion Gain
G-Y/B-Y Matrix Ratio
G-Y/R-Y Matrix Ratio
Sub-Carrier and Harmonic Content at Outputs No Chroma or Luma Input. Read residual carrier at outputs.
SANDCASTLE PULSE
Horizontal and Vertical Blanking Pedestal
Burst Gate Pulse
1. If a different value is desired, see the Threshold Adjustment Circuit of Figure 17.
2. Use of the circuit of Figure 18 is suggested to prevent increased color saturation at low level RF signals.
3. The reference voltage can be adjusted by changing the values of the voltage divider.
PARAMETER
(See Block Diagram and Figure 20)
T
for F
These conditions exist except as otherwise noted. See Figure 19 for test circuit (Continued)
A
= +25
OSC
o
= 4.43361875MHz, Sandcastle: V
C, V
CC
For control characteristic, see Figure 10.
Chroma Input: Burst = 100mV
Adjust V
Chroma Input: Burst = 100mV
Adjust C
Apply signal to lock.
Chroma Input: Burst =100mV, Chroma = 220mV
Adjust V
Chroma Input: Burst = 100mV
Calculate V16/V14. V
Chroma Input: Burst =100mV
read V17 and V16, Calculate V17/V16. V
Chroma Input: Burst =100mV
Read V17 and V18. Calculate V17/V18. V
= 12V, V
Specifications CA3194
C
C
X
S
and V
for HI/LO f
for V18 = 1V. Read V15. Calculate V18/V15.
= 2.85V, V
S
for maximum Pin 2 output.
7-58
TEST CONDITIONS
OSC
C
C
A buffer stage drives the external PAL delay line. The sepa-
rated U and V signals are applied to pins 14 and 15, respec-
tively, and demodulated. A standard G-Y matrix is included
on the chip.
The luminance signal passes through the subcarrier trap
and through the luminance delay line and enters the chip at
pin 20. Contrast and brightness control is provided before
the luminance signal is combined with the color difference
signals in the Y matrix. Average and peak beam limiting cir-
cuits are controlled from pins 24 and 19.
remains as for R-Y gain.
= 2.85V, V
without Chroma signal.
BG
P-P
P-P
P-P
P-P
P-P
= 8.0V, V
, Chroma = 220mV
, Chroma = 220mV
, Chroma = 220mV
, Chroma = 220mV
, U
AB
ø
= V
. Read V16 and V14.
BLANK
PB
C
C
remains as above.
= V
remains as above.
CC
= 3.5V - Burst Gate centered on Burst.
P-P
, V
,V
P-P
P-P
B
P-P
P-P
adjusted for V
ø
, U
, V
.
.
.
ø
ø
.
TYPICAL
6.5 - V
VALUE
18
0 - 5
2 - 5
2.5
0.2
0.5
500
10
18
30
2
= 6.3V, C
CC
X
UNITS
100Hz
mV
Deg./
Ratio
Ratio
Ratio
Ratio
adjusted
V
V
Hz
P-P
V
V
DC
P-P
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