CS1089 ON Semiconductor, CS1089 Datasheet - Page 5

• Manufacturer Part Number: CS1089
• Description: Vacuum Fluorescent Display Tube Driver
• Manufacturer: ON Semiconductor

GREN
GND
CLK
STB
V
D
BB
IN
function will cause all of the anode and grid driver outputs
to be off and all shift register outputs to be set low. Data is
fed into the shift register through the D
edge of the CLK input. Thirty two bits of data are capable of
being stored by the shift register. Once the desired pattern is
stored in the shift register, it can be transferred to the latch
by setting the STB input high. The output of each latch
drives its corresponding output stage. A logic high input to
the shift register/latch will cause the corresponding output
to turn on. A logic low input to the shift register/latch will
cause the corresponding output to turn off. Please note that
if the STB is held high, the outputs of the latch reflect the
outputs of the corresponding shift register bits and will
change if data is shifted in.
POR
V
V
V
V
REG
REG
REG
REG
Upon the initial application of power, the power on reset
V
REG
D Q
V
CLK
REG
R
D Q
LE
D Q
CLK
GRID1 GRID2 GRID3
R
Output Drive Capability
Grid Outputs: 5 mA
AN24 – AN29: 20 mA
AN1 – AN23: 2.0 mA
D Q
CLK
D Q
LE
R
D Q
D Q
LE
CLK
R
D Q
D Q
LE
CLK
IN
R
AN1
pin at the rising
OPERATION DESCRIPTION
D Q
D Q
LE
CLK
R
AN2
Figure 2. Block Diagram
http://onsemi.com
D Q
LE
AN3
METAL MASK ROM
CS1089
D Q
CLK
5
R
When GREN is low, the GRID outputs are forced low
regardless of the state of the corresponding latch output.
When GREN is high, the GRID outputs correspond to the
state of their respective latch outputs. The anode outputs,
AN1 to AN29 are always enabled.
register to allow serial cascading of this IC with other
devices. Data from the last stage of the shift register is
supplied to the D
the D
to prevent logic race conditions between the CLK and the
D
IN
D Q
The three GRID outputs are gated by the GREN input.
The D
CLK
R
AN23
D Q
LE
of the next IC in the serial chain.
OUT
OUT
D Q
CLK
output changes with the falling edges of the CLK
AN24
D Q
LE
R
pin is the output of the last stage of the shift
OUT
D Q
CLK
AN25
D Q
LE
R
pin delayed by 1/2 CLK cycle. Data on
D Q
CLK
AN26
D Q
LE
R
D Q
AN27
D Q
LE
CLK
R
D Q
LE
AN28
D Q
CLK
R
AN29
D Q
LE
D Q
CLK
R
V
REG
D
OUT