ST9291 ST Microelectronics, ST9291 Datasheet - Page 15

• Manufacturer Part Number: ST9291
• Description: 16-48K ROM HCMOS MCU WITH ON SCREEN DISPLAY AND VOLTAGE TUNINGOUTPUT
• Manufacturer: ST Microelectronics

SYSTEM REGISTERS (Continued)
1.1.3.4 Page Configuration
The pages are available to be used for the storage
of control information (such as interrupt vector
pointers) relevant to particular peripherals. There
are up to 64 pages (each with 16 registers) based
on registers R240-R255. These paged registers
are addressable via the page pointer register
(PPR), which is system register R234.
To address a paged register the page pointer regis-
ter (R234) must be loaded with the relevant page
number using the spp instruction (Set Page Pointer)
and subsequently any address from the top (F)
group (R240-R255) will be referred to that page.
For example if register 23 contains the value 44,
the following sequence loads the third register
R242 on page 5 with the value 44.
spp 5
ld R242, R23
PPR R234 (EAh) System Read/Write
Page Pointer Register
Reset value : undefined
b7-b2 = PP7-PP2: Page Pointer . These bits con-
tain the number (between 0 to 63) of the page cho-
sen by the instruction ssp (Set Page Pointer). PP7
is the MSB of the page address. Once the page
pointer has been set, there is no need to refresh it
unless a different page is required.
b1-b0 = D1,D0: These bits are fixed by hardware to
zero and are not affected by any writing instruction
trying to modify their value.
PAGE 0 contains the control registers of:
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-
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the external interrupt
the watchdog timer
the wait logic states
the serial peripheral interface (SPI)
1.1.3.5 Mode Registers
This register MODER is located in the System
Register Group at the address 235.
Using this register it is possible:
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MODER R235 (EBh) System Read/Write
Mode Register
Reset value : 1110 0000
b7 = SSP: System Stack Pointer . This bit selects
internal (in the Register File) or external (in the ex-
ternal Data Memory) System Stack area, logical
“1” for internal, and logical “0” for external. After
Reset the value of this bit is “1”.
b6 = USP: User Stack Pointer . Same as bit 7 for
the User Stack Pointer;
b5 = DIV2: OSCIN Clock Divided by 2 . This bit con-
trols the divide by 2 circuit which operates on the
OSCIN Clock. A logical “1” value means that the
OSCIN clock is internally divided by 2, and a logical
“0” value means that no division of the OSCIN
Clock occurs.
b4-b2 = PRS2-PRS0: ST9 CPUCLK Prescaler .
These bits load the prescaling module of the inter-
nal clock (INTCLK). The prescaling value selects
the frequency of the ST9 clock, which can be di-
vided by 1 to 8. See Clock chapter for more infor-
mation.
b1 = BRQEN: Bus Request Enable . This bit must
be held to “0”.
b0 = HIMP: High Impedance Enable . This bit must
be held to “0”.
to select either internal or external System and
User Stack area,
to manage the clock frequency
to enable the Bus request and Wait signals
when interfacing external memory.
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