ST9291 ST Microelectronics, ST9291 Datasheet - Page 7

• Manufacturer Part Number: ST9291
• Description: 16-48K ROM HCMOS MCU WITH ON SCREEN DISPLAY AND VOLTAGE TUNINGOUTPUT
• Manufacturer: ST Microelectronics

1 CORE DESCRIPTION
1.1 CORE ARCHITECTURE
1.1.1 INTRODUCTION
The Core or Central Processing Unit (CPU) of the
ST9 includes the 8 bit Arithmetic Logic Unit and the
16 bit Program Counter, System and User Stack
Pointers. The microcoded Instruction Set is highly
optimised for both byte (8 bit) and word (16 bit)
data, BCD and Boolean data types, with 14 ad-
dressing modes.
Three independent buses are controlled by the
Core, a 16 bit Memory bus, an 8 bit Register ad-
dressing bus and a 6 bit Interrupt/DMA bus con-
nected to the interrupt and DMA controllers in the
on-chip peripherals and the Core. This multiple bus
architecture allows a high degree of pipelining and
parallel operation, giving the ST9 its efficiency in
both numerical calculations and communication
with the on-chip peripherals.
Figure 1-4. Address Spaces
PROGRAM
MEMORY
64K
REGISTER
FILE
1.1.2 ADDRESS SPACES
The ST9 has three separate address spaces:
-
-
-
The Data and Program memory spaces will be ad-
dressed in further detail in section 1.3.
1.1.2.1 Register File
The Register File consists of:
-
-
-
Register File: 240 8-bit registers plus up to 64
pages of 16 bytes each, located in the on-chip
peripherals.
Data memory with up to 64K (65536) bytes
Program memory with up to 64K (65536) bytes
224 general purpose registers R0 to R223
16 system registers in the System Group
(R224 to R239).
I/O pages depending on the configuration of
the ST9, each containing up to 16 registers,
with paging facilities based on the top group
(R240 to R255).
MEMORY
DATA
64K
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