CY7C4235-15AC Cypress Semiconductor Corp, CY7C4235-15AC Datasheet - Page 10
![IC SYNC FIFO MEM 2KX18 64LQFP](/photos/6/76/67621/428-64-tqfp_sml.jpg)
CY7C4235-15AC
Manufacturer Part Number
CY7C4235-15AC
Description
IC SYNC FIFO MEM 2KX18 64LQFP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Specifications of CY7C4235-15AC
Function
Synchronous
Memory Size
36K (2K x 18)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Configuration
Dual
Density
36Kb
Access Time (max)
10ns
Word Size
18b
Organization
2Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
45mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1221
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C4235-15AC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C4235-15AC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Switching Characteristics
Switching Waveforms
Note
Document Number: 001-45652 Rev. **
t
t
t
t
t
t
t
18. t
HF
XO
XI
XIS
SKEW1
SKEW2
SKEW3
Parameter
the rising edge of RCLK and the rising edge of WCLK is less than t
SKEW1
WCLK
RCLK
–D
WEN
REN
FF
17
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between
Clock to Half-Full Flag
Clock to Expansion Out
Expansion in Pulse Width
Expansion in Set-up Time
Skew Time between Read Clock and Write Clock
for Full Flag
Skew Time between Read Clock and Write Clock
for Empty Flag
Skew Time between Read Clock and Write Clock
for Programmable Almost Empty and Program-
mable Almost Full Flags.
t
SKEW1
Description
Over the Operating Range (continued)
t
[18]
CLKH
t
WFF
t
CLK
Figure 6. Write Cycle Timing
t
DS
SKEW1
t
CLKL
t
ENS
, then FF may not change state until the next WCLK edge.
Min.
4.5
10
3
5
5
-10
Max.
t
DH
12
t
ENH
7
t
WFF
Min.
6.5
15
5
6
6
-15
Max.
16
10
NO OPERATION
CY7C4425/4205/4215
CY7C4225/4235/4245
Min.
10
10
10
10
18
-25
Max.
20
15
Min.
14
15
12
12
20
-35
Page 10 of 22
Max.
25
20
Unit
ns
ns
ns
ns
ns
ns
ns
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