CY7C4291-10JC Cypress Semiconductor Corp, CY7C4291-10JC Datasheet - Page 5
![IC DEEP SYNC FIFO 128KX9 32-PLCC](/photos/6/51/65138/428-32-plcc_sml.jpg)
CY7C4291-10JC
Manufacturer Part Number
CY7C4291-10JC
Description
IC DEEP SYNC FIFO 128KX9 32-PLCC
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheet
1.CY7C4291-10JC.pdf
(16 pages)
Specifications of CY7C4291-10JC
Function
Synchronous
Memory Size
1.1M (128K x 9)
Data Rate
100MHz
Access Time
8ns
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-PLCC
Configuration
Dual
Density
1.125Mb
Access Time (max)
8ns
Word Size
9b
Organization
128Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
PLCC
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
40mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1244
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C4291-10JC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-06007 Rev. *B
Notes:
WRITE ENABLE 1(WEN1)
2.
3.
WRITE ENABLE 2/LOAD
PROGRAMMABLE(PAF)
DATA IN (D)
WRITECLOCK (WCLK)
Figure 2. Block Diagram of 64k x 9/128k x 9 Deep Sync FIFO Memory Used in a Width Expansion Configuration
n = Empty Offset (n = 7 default value).
m = Full Offset (m = 7 default value).
FULL FLAG (FF) # 1
FULL FLAG (FF) # 2
(WEN2/LD)
18
9
Read Enable 2 (REN2)
FF
CY7C4281/91
RESET (RS)
EF
9
9
Read Enable 2 (REN2)
FF
CY7C4281/91
RESET (RS)
EF
EMPTY FLAG (EF) #2
EMPTY FLAG (EF) #1
9
READ CLOCK (RCLK)
READ ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
PROGRAMMABLE(PAE)
DATA OUT (Q)
CY7C4281
CY7C4291
Page 5 of 16
18