AD9518-2 Analog Devices, Inc., AD9518-2 Datasheet - Page 33

• Manufacturer Part Number: AD9518-2
• Description: 6-output Clock Generator With Integrated 2.2 Ghz Vco
• Manufacturer: Analog Devices, Inc.

Once in holdover mode, the charge pump stays in a high
impedance state as long as there is no reference clock present.
As in the external holdover mode, the B counter (in the N divider)
is reset synchronously with the charge pump leaving the high
impedance state on the reference path PFD event. This helps to
align the edges out of the R and N dividers for faster settling of
the PLL and to reduce frequency errors during settling. Because
the prescaler is not reset, this feature works best when the B and
R numbers are close, resulting in a smaller phase difference for
the loop to settle out.
After leaving holdover, the loop then reacquires lock and the
LD pin must charge (if 0x1D<3> = 1b) before it can re-enter
holdover (CP high impedance).
The holdover function always responds to the state of the
currently selected reference (0x1C). If the loop loses lock during
a reference switchover (see the Reference Switchover section),
holdover is triggered briefly until the next reference clock edge
at the PFD.
The following registers affect the automatic/internal holdover
function:
• 0x18<6:5>—lock detect counter. This changes how many
• 0x18<3>—disable digital lock detect. This bit must be set to 0
• 0x1A<5:0>—LD pin control. Set this to 000100b to put it in
• 0x1D<3>—LD pin comparator enable. 1 = enable; 0 =
• 0x1D<1>—external holdover control.
• 0x1D<0> and 0x1D<2>—holdover enable. If holdover is
consecutive PFD cycles with edges inside the lock detect
window are required for the DLD indicator to indicate lock.
This impacts the time required before the LD pin can begin
to charge as well as the delay from the end of a holdover
event until the holdover function can be re-engaged.
to enable the DLD circuit. Automatic/internal holdover does
not operate correctly without the DLD function enabled.
the current source lock detect mode if using the LD pin
comparator. Load the LD pin with a capacitor of an
appropriate value.
disable. When disabled, the holdover function always senses
the LD pin as high.
disabled, both external and automatic/internal holdover are
disabled.
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For example, to use automatic holdover with:
• Automatic reference switchover, prefer REF1.
• Digital lock detect: five PFD cycles, high range window.
• Automatic holdover using the LD pin comparator.
The following registers are set (in addition to the normal PLL
registers):
• 0x18<6:5> = 00b; lock detect counter = five cycles.
• 0x18<4> = 0b; lock detect window = high range.
• 0x18<3> = 0b; DLD normal operation.
• 0x1A<5:0> = 000100b; current source lock detect mode.
• 0x1C<4> = 1b; automatic reference switchover enabled.
• 0x1C<3> = 0b; prefer REF1.
• 0x1C<2:1> = 11b; enable REF1 and REF2 input buffers.
• 0x1D<3> = 1b; enable LD pin comparator.
• 0x1D<2> = 1b; enable the holdover function.
• 0x1D<1> = 0b; use internal/automatic holdover mode.
• 0x1D<0> = 1b; enable the holdover function.
Frequency Status Monitors
The AD9518 contains three frequency status monitors that are
used to indicate if the PLL reference (or references in the case of
single-ended mode) and the VCO have fallen below a threshold
frequency. A diagram showing their location in the PLL is
shown in Figure 37.
The PLL reference monitors have two threshold frequencies:
normal and extended (see Table 15). The reference frequency
monitor thresholds are selected in 0x1F.
AD9518-2