AD9518-2 Analog Devices, Inc., AD9518-2 Datasheet - Page 59

• Manufacturer Part Number: AD9518-2
• Description: 6-output Clock Generator With Integrated 2.2 Ghz Vco
• Manufacturer: Analog Devices, Inc.

Reg.
Addr
(Hex) Bit(s) Name
196
196
197
197
197
197
197
198
198
Reg.
Addr
(Hex) Bit(s) Name
1E0
1E1
1E1
1E1
Table 46. VCO Divider and CLK Input
<2:0> VCO Divider
<4>
<3>
<2>
<7:4> Divider 2 Low Cycles
<3:0> Divider 2 High Cycles
<7>
<6>
<5>
<4>
<3:0> Divider 2 Phase Offset
<1>
<0>
Power-Down Clock Input Section Power down the clock input section (including CLK buffer, VCO divider, and CLK tree).
Power-Down VCO Clock Interface Power down the interface block between VCO and clock distribution.
Power-Down VCO and CLK
Divider 2 Bypass
Divider 2 Nosync
Divider 2 Force High
Divider 2 Start High
Divider 2 Direct to Output
Divider 2 DCCOFF
Description
Number of clock cycles of the divider input during which divider output stays low.
Number of clock cycles of the divider input during which divider output stays high.
Bypasses and powers down the divider; route input to divider output.
<7> = 0; use divider.
<7> = 1; bypass divider.
Nosync.
<6> = 0; obey chip-level SYNC signal.
<6> = 1; ignore chip-level SYNC signal.
Forces divider output to high. This requires that nosync also be set.
<5> = 0; divider output forced to low.
<5> = 1; divider output forced to high.
Selects clock output to start high or start low.
<4> = 0; start low.
<4> = 1; start high.
Phase offset.
Connect OUT4 and OUT5 to Divider 2 or directly to VCO or CLK.
<1> = 0; OUT4 and OUT5 are connected to Divider 2.
<1> = 1;
If 0x1E1<1:0> = 10b, the VCO is routed directly to OUT4 and OUT5.
If 0x1E1<1:0> = 00b, the CLK is routed directly to OUT4 and OUT5.
If 0x1E1<1:0> = 01b, there is no effect.
Duty-cycle correction function.
<0> = 0; enable duty-cycle correction.
<0> = 1; disable duty-cycle correction.
Description
<2>
0
0
0
0
1
1
1
1
<4> = 0; normal operation.
<4> = 1; power-down.
<3> = 0; normal operation.
<3> = 1; power-down.
Power down both VCO and CLK input.
<2> = 0; normal operation.
<2> = 1; power-down.
Rev. 0 | Page 59 of 64
<1>
0
0
1
1
0
0
1
1
<0>
0
1
0
1
0
1
0
1
Divide
2
3
4
5
6
Output static
Output static
Output static
AD9518-2