AD9520-4 Analog Devices, Inc., AD9520-4 Datasheet - Page 40
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AD9520-4
Manufacturer Part Number
AD9520-4
Description
12 Lvpecl/24 Cmos Output Clock Generator With Integrated 1.6 Ghz Vco
Manufacturer
Analog Devices, Inc.
Datasheet
1.AD9520-4.pdf
(84 pages)
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AD9520-4
The holdover function senses the logic level of the LD pin as a
condition to enter holdover. The signal at LD can be from the
DLD, ALD, or current source LD mode. It is possible to disable
the LD comparator (0x01D[3]), which causes the holdover
function to always sense LD as being high. If DLD is used, it is
possible for the DLD signal to chatter while the PLL is
reacquiring lock. The holdover function may retrigger, thereby
preventing the holdover mode from terminating. Use of the
current source lock detect mode is recommended to avoid this
situation (see the Current Source Digital Lock Detect section).
HIGH IMPEDANCE
HIGH IMPEDANCE
WHEN DLD WENT
LD PIN == HIGH
CHARGE PUMP
CHARGE PUMP
EDGE AT PFD?
PLL ENABLED
DLD == HIGH
DLD == LOW
REFERENCE
RELEASE
LOW?
WAS
YES
YES
YES
YES
YES
Figure 44. Flowchart of Automatic/Internal Holdover Mode
NO
NO
NO
NO
YES
Rev. 0 | Page 40 of 84
LOOP OUT OF LOCK. DIGITAL LOCK
DETECT SIGNAL GOES LOW WHEN THE
LOOP LEAVES LOCK AS DETERMINED
BY THE PHASE DIFFERENCE AT THE
INPUT OF THE PFD.
ANALOG LOCK DETECT PIN INDICATES
LOCK WAS PREVIOUSLY ACHIEVED.
(0x01D<3> = 1; USE LD PIN VOLTAGE
WITH HOLDOVER.
0x01D<3> = 0; IGNORE LD PIN VOLTAGE,
TREAT LD PIN AS ALWAYS HIGH.)
CHARGE PUMP IS MADE
HIGH IMPEDANCE.
PLL COUNTERS CONTINUE
OPERATING NORMALLY.
CHARGE PUMP REMAINS HIGH
IMPEDANCE UNTIL THE REFERENCE
HAS RETURNED.
TAKE CHARGE PUMP OUT OF
HIGH IMPEDANCE. PLL CAN
NOW RESETTLE.
WAIT FOR DLD TO GO HIGH. THIS TAKES
5 TO 255 CYCLES (PROGRAMMING OF THE DLD
DELAY COUNTER) WITH THE REFERENCE AND
FEEDBACK CLOCKS INSIDE THE LOCK WINDOW AT
THE PFD. THIS ENSURES THAT THE HOLDOVER
FUNCTION WAITS FOR THE PLL TO SETTLE AND LOCK
BEFORE THE HOLDOVER FUNCTION CAN BE
RETRIGGERED.
Once in holdover mode, the charge pump stays in a high
impedance state as long as there is no reference clock present.
As in the external holdover mode, the B counter (in the N divider)
is reset synchronously with the charge pump leaving high
impedance state on the reference path PFD event. This helps
align the edges out of the R and N dividers for faster settling of
the PLL and reduces frequency errors during settling. Because
the prescaler is not reset, this feature works best when the B and
R numbers are close because this results in a smaller phase
difference for the loop to settle out.