AD9634BCPZRL7-250 Analog Devices, Inc., AD9634BCPZRL7-250 Datasheet - Page 6

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AD9634BCPZRL7-250

Manufacturer Part Number
AD9634BCPZRL7-250
Description
12-bit, 170 Msps/210 Msps/250 Msps, 1.8 V Analog-to-digital Converter
Manufacturer
Analog Devices, Inc.
Datasheet
AD9634
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless
otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
LOGIC INPUT (CSB)
LOGIC INPUT (SCLK)
LOGIC INPUTS (SDIO)
DIGITAL OUTPUTS
1
2
Pull-up.
Pull-down.
LVDS Data and OR Outputs (OR+, OR−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
Differential Output Voltage (V
Output Offset Voltage (V
Differential Output Voltage (V
Output Offset Voltage (V
1
2
1
OS
OS
), ANSI Mode
), Reduced Swing Mode
OD
OD
), ANSI Mode
), Reduced Swing Mode
Rev. 0 | Page 6 of 32
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
0.3
AGND
0.9
10
−22
12
1.22
0
50
−5
1.22
0
45
−5
1.22
0
45
−5
250
1.15
150
1.15
CMOS/LVDS/LVPECL
Typ
0.9
4
15
26
2
26
2
26
5
350
1.25
200
1.25
Max
3.6
AVDD
1.4
22
−10
18
2.1
0.6
71
+5
2.1
0.6
70
+5
2.1
0.6
70
+5
450
1.35
280
1.35
Unit
V
V p-p
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
mV
V
mV
V

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