AD9260-EB Analog Devices, Inc., AD9260-EB Datasheet
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AD9260-EB
Related parts for AD9260-EB
AD9260-EB Summary of contents
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... Single Supply—Both the analog and digital portions of the AD9260 can operate off of a single +5 V supply, simplifying system power supply design. The digital logic will also accommodate a single +3 V supply for reduced power. ...
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... AD9260 TABLE OF CONTENTS Specifications..................................................................................... 3 Clock Input Frequency Range .................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 4 Digital Filter Characteristics ....................................................... 6 Digital Filter Characteristics ....................................................... 7 Digital Specifications ................................................................... 9 Switching Specifications ............................................................ 10 Absolute Maximum Ratings.......................................................... 11 Thermal Characteristics ............................................................ 11 ESD Caution................................................................................ 11 Terminology .................................................................................... 12 Pin Configuration and Function Descriptions........................... 13 Typical Performance Characteristics ........................................... 14 Typical AC Characterization Curves vs. Decimation Mode ................................................................. 15 Typical AC Characterization Curves for 8× ...
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... Rev Page AD9260 (2) AD9260 (1) Unit 1 1 kHz min 20 20 MHz max 0.500 1 kHz min 10 20 MHz max to T unless otherwise noted, MIN MAX AD9260 (1) Unit 12 Bits min 1.3 LSB rms typ 1 ...
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... POWER CONSUMPTION 1 VINA and VINB connect to DUT CML. 2 Including Internal 2.5 V reference. 3 Excluding Internal 2.5 V reference. 4 Load regulation with 1 mA load current (in addition to that required by AD9260). AC SPECIFICATIONS AVDD = +5 V, DVDD = +3 V, DRVDD = + kΩ. BIAS Table 3. Parameter—Decimation Factor (N) DYNAMIC PERFORMANCE ...
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... Rev Page AD9260 AD9260(1) Unit 82 dB typ 63 dB typ 58 dB typ 63 dB typ 58 dB typ –79 dB typ –77 dB typ 80 dB typ 80 dB typ 63 dB typ 58 dB typ ...
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... PROP Absolute Group Delay 1 To determine overall Absolute Group Delay and/or Settling Time inclusive of delay from the sigma-delta modulator, add Absolute Group Delay and/or Settling Time pertaining to specific decimation mode to the Absolute Group Delay specified in 1 ×decimation. AD9260 0.00125 82.5 0 0.605 × (f ...
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... CLOCK PERIODS (RELATIVE TO CLK) Figure 5. 8x FIR Filter Impulse Response 1.0 0.8 0.6 0.4 0 CLOCK PERIODS (RELATIVE TO CLK) Figure 6. 4x FIR Filter Impulse Response 1.0 0.8 0.6 0.4 0 CLOCK PERIODS (RELATIVE TO CLK) Figure 7. 2x FIR Filter Impulse Response AD9260 500 600 90 100 110 20 25 ...
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... AD9260 Table 5. Integer Filter Coefficients for First Stage Decimation Filter (23-Tap Half-Band FIR Filter) Lower Coefficient Upper Coefficient H(1) H(23) H(2) H(22) H(3) H(21) H(4) H(20) H(5) H(19) H(6) H(18) H(7) H(17) H(8) H(16) H(9) H(15) H(10) H(14) H(11) H(13) H(12) Table 6. Integer Filter Coefficients for Second Stage Decimation Filter (43-Tap Half-Band FIR Filter) Lower Coefficient Upper Coefficient H(1) H(43) H(2) H(42) H(3) H(41) H(4) H(40) H(5) H(39) H(6) H(38) H(7) H(37) H(8) H(36) H(9) H(35) H(10) H(34) H(11) H(33) H(12) H(32) H(13) H(31) H(14) H(30) H(15) H(29) H(16) H(28) H(17) H(27) H(18) H(26) H(19) H(25) H(20) H(24) H(21) H(23) H(22) NOTE: The composite filter undecimated coefficients (i.e., impulse response) in the 4× ...
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... LOGIC OUTPUTS (with DRVDD = 3 V) High Level Output Voltage ( µA) OH Low Level Output Voltage ( µ Since CLK is referenced to AVDD logic input levels only apply. 2 The AD9260 is not guaranteed to meet V = 0.4 V max for standard TTL load ANALOG INPUT ...
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... MIN MAX Symbol DAV RES–DAV t CLK–DAV Rev Page AD9260 Unit 50 ns min t ×Mode ns min C 40 max DAV t –t –t ns min DAV H DI 22.5 ns min 22.5 ns min 3.5 ns min 10 ns typ 15 ...
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... V to +0.3 V Thermal Resistance –0 DVDD + 0.3 V 44-Lead MQFP θ = 53.2°C/W –0 DRVDD + 0 θ = 19°C/W –0 AVDD + 0 –0 AVDD + 0.3 V –0 AVDD + 0.3 V –0 AVDD + 0.3 V 150°C –65°C to +150°C 300°C Rev Page AD9260 ...
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... NOTE: Conventional INL and DNL measurements don’t really apply to ∑∆ converters: the DNL looks continually better if longer data records are taken. For the AD9260, INL and DNL numbers are given as representative. Zero Error The major carry transition should occur for an analog value 1/2 LSB below VINA = VINB ...
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... Noise Reduction Pin—Decouples Reference Level. Common-Mode Level (AVDD/2.5). No Connect (Ground for Shielding Purposes). Analog Input Pin (+). Analog Input Pin (–). Rev Page REFCOM 32 VREF 31 SENSE 30 RESET 29 AVSS 28 AVDD DAV OTR 25 24 BIT1 (MSB) 23 BIT2 21 22 AD9260 ...
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... DECIMATION THD: –98dB –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 14. Spectral Plot of the AD9260 at 100 kHz Input, 20 MHz Clock, Undecimated (20 MHz Output Data Rate) 110 –12dBFS/TONE 106 102 –6.5dBFS/TONE 98 –26dBFS/TONE –46dBFS/TONE 0.2 0.4 0.6 FREQUENCY (MHz) Figure 15 ...
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... INPUT FREQUENCY (MHz) Figure 21. THD vs. Input Frequency (f CLOCK –70 –75 1 × MODE –80 –85 –90 2 × MODE –95 4 × MODE –100 8 × MODE –105 –110 –115 –120 0.1 1.0 INPUT FREQUENCY (MHz) Figure 22. SFDR vs. Input Frequency (f CLOCK AD9260 10 MSPS) 10 MSPS) 10 MSPS) ...
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... AD9260 TYPICAL AC CHARACTERIZATION CURVES FOR 8× MODE AVDD = DVDD = DRVDD = + Input Span, Differential DC Coupled Input with CML = 2 V, Full Bias –0.5dBFS –6.0dBFS –20dBFS 65 60 0.1 INPUT FREQUENCY (MHz) Figure 23. SINAD vs. Input Frequency (f CLOCK limited by noise contribution of input differential op amp driver. ...
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... INPUT FREQUENCY (MHz) Figure 32. SINAD vs. Input Frequency ( MSPS) CLOCK –0.5dBFS –6.0dBFS 0.1 INPUT FREQUENCY (MHz) Figure 33. THD vs. Input Frequency ( MSPS) CLOCK –6.0dBFS –0.5dBFS 0.1 INPUT FREQUENCY (MHz) Figure 34. SFDR vs. Input Frequency ( MSPS) CLOCK AD9260 1.0 –20dBFS 1.0 –20dBFS 1.0 ...
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... AD9260 TYPICAL AC CHARACTERIZATION CURVES FOR 2× MODE AVDD = DVDD = DRVDD = + Input Span, Differential DC Coupled Input with CML = 2 V, Full Bias 0.1 1.0 INPUT FREQUENCY (MHz) Figure 35. SINAD vs. Input Frequency (f –60 –65 –70 –75 –0.5dBFS –80 –85 –90 – ...
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... INPUT FREQUENCY (MHz) Figure 44. SINAD vs. Input Frequency ( MSPS) CLOCK –20dBFS –0.5dBFS –6.0dBFS 0.1 1.0 INPUT FREQUENCY (MHz) Figure 45. THD vs. Input Frequency ( MSPS) CLOCK –0.5dBFS –6.0dBFS –20dBFS 0.1 1.0 INPUT FREQUENCY (MHz) Figure 46. SFDR vs. Input Frequency ( MSPS) CLOCK AD9260 10.0 10.0 10.0 ...
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... AD9260 TYPICAL AC CHARACTERIZATION CURVES AVDD = DVDD = DRVDD = + Input Span, A 100 QUARTER BIAS CLOCK FREQUENCY (MHz) Figure 47. SFDR vs. Clock Rate (f 100 80 60 QUARTER BIAS CLOCK FREQUENCY (MHz) Figure 48. SFDR vs. Clock Rate (f ...
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... F = 1.05 MHz, 8x Mode, 20 MSPS 120 110 100 –60 –50 –40 –30 –20 A (dBFS) IN Figure 58. Two-Tone SFDR (F = 1.9 MHz 2.1 MHz, 4x Mode 20 MSPS AD9260 20 MSPS (dBFS) FULL BIAS 10 MSPS (dBc) HALF BIAS – 525 MHz, 8x Mode) 2 –10 0 dBFS dBc –10 0 ...
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... AD9260 + V INT1 IN – 5B DAC1 + 16 – INT2 – ADC DAC ADC 5B DAC2 M OUT –D SHUFFLE Z CONTROL/TEST LOGIC DECIMATION FILTER STAGE 1 BANDGAP REFERENCE DECIMATION FILTER STAGE 2 REFERENCE BUFFER DECIMATION FILTER STAGE 3 Figure 59. Simplified Block Diagram Rev Page – – ...
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... The combination of a second order loop and multibit feedback provides inherent stability: the AD9260 is not prone to the idle tones or full-scale idiosyncrasies sometimes associated with higher order single bit sigma-delta modulators. ...
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... Figure 63 is sufficient for protecting the AD9260 in an undervoltage condition. For additional information showing the relationships between VINA, VINB, VREF, and the digital output of the AD9260, see Table 13. Refer to Table 12 for a summary of the various analog input and reference configurations. ...
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... The analog circuitry used to drive the input pins of the AD9260 must respond to the charge glitch that occurs when capacitors CS1 and CS2 are connected to input pins VINA and VINB. This ...
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... V p-p single-ended, ground-referenced signal p-p differential signal centered at the common-mode level of the AD9260. The circuit is based on two op amps that are configured as matched unity gain difference amplifiers. The single-ended input signal is applied to opposing inputs of the difference amplifiers, thus providing differential outputs ...
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... Note: the common-mode voltage of the input signal applied to the AD9260 need not be at the exact same level as CML. While this level is recommended for optimal performance, the AD9260 is tolerant of a range of input common-mode voltages around AVDD/2 ...
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... AD9260 REFERENCE OPERATION The AD9260 contains an on-board band gap reference and internal reference buffer amplifier. The onboard reference provides a pin-strappable option to generate either 2.5 V output. With the addition of two external resistors, the user can generate reference voltages other than 1 V and 2.5 V. ...
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... The actual reference voltages used by the internal circuitry of the AD9260 appear on the CAPT and CAPB pins. If VREF is configured for 2.5 V, thus providing full-scale input span, the voltages appear at CAPT and CAPB are 3.0 V and 1.0 V respectively. For proper operation when using the internal or an external reference necessary to add a capacitor network to decouple the CAPT and CAPB pins ...
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... High High Digital Output DAV Pin 1000 0000 0000 0000 The DAV pin indicates when the output data of the AD9260 is 1000 0000 0000 0000 valid. Digital output data is updated on the rising edge of DAV. 0000 0000 0000 0000 The data hold time (t 0111 1111 1111 1111 DAV and the digital data output pins (BIT1– ...
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... CLK). In order to synchronize multiple AD9260s clocked with the same clock necessary that the clock dividers in each of the individual AD9260s are all reset to the same state. When RESET is asserted low, these clock dividers are cleared. On the next falling edge of CLK following the rising edge of RESET , the clock dividers begin counting and the clock is applied to the digital decimation filters ...
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... Refer to the characterization curves shown in Figure 47 to Figure 54 revealing the performance tradeoffs. The scaling is accomplished by properly attaching an external resistor to the BIAS pin of the AD9260 as shown in Table 17 normally 2 kΩ for a clock speed of 20 MHz and scales EXT inversely with clock rate ...
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... Switching Specifications at the beginning of the data sheet to meet the rated performance specifications. For 1 × MODE example, the clock input to the AD9260 operating at 20 MSPS 2 × MODE may have a duty cycle between 45% and 55% to meet this timing requirement since the minimum specified t 22 ...
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... Note that the AVDD and AVSS pins are co-located on the AD9260 to simplify the layout of the decoupling capacitors and provide the shortest possible PCB trace lengths. The AD9260/EB power plane layout, shown in Figure 84 depicts a typical arrangement using a multilayer PCB ...
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... AD9260 supply pins. Further noise immunity from noise is provided by the inherent power supply rejection of the AD9260 as shown in Figure 70. If digital operation desirable for power savings and or to provide for digital logic interface linear regulator can be used to drive DVDD and/or DRVDD ...
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... The power consumption of the AD9260 can be scaled down if the user is able to operate the device at a lower clock frequency. As illustrated in Figure 78, pin cups are provided for the external resistor (R2) tied to the BIAS pin of the AD9260. Table 17 defines the recommended resistance for a given clock speed to obtain the desired power consumption. ...
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... U9) that configure the input into a differential signal and drive it, through a pair of isolation resistors, into the input pins of AD9260. The user can either input a signal or dual signal into the evaluation board via the two SMA connectors (J6 and J7) labeled IN-1 or IN-2. ...
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... FFT testing. A low jitter clock may be generated by using a high- frequency clock source and dividing this frequency down with a low noise clock divider to obtain the AD9260 input CLK. Maintaining a large amplitude clock signal may also be very beneficial in minimizing the effects of noise in the digital gates of the clock generation circuitry ...
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... BIT02 BIT14 BIT01(MSB) BIT15 OTR BIT16(LSB) DAV READ CS CLK MDAVDD AVDD DRVDD AVSS DRVSS AVDD RESET DVDD SENSE AVSS VREF DVSS REFCOM Figure 78. Evaluation Board Top Level Schematic Rev Page AD9260 RD SHIELDED_TRACE FLAVDD DVDD ...
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... AD9260 R21 J6 390Ω IN-2 R1 57.6Ω J7 IN-1 R15 57.6Ω 390Ω IKPOT R35 1kΩ 0.1µF 1 P4:+5V + C36 10mF C37 0.1mF + C40 10µF C41 0.1µF + C44 10µF C45 0.1µ P3:D5 + C32 22µF C33 0.1µ EVALUATION BOARD POWER SUPPLY CONFIGURATION R18 390Ω C20 0.1µF ...
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... Figure 81. Evaluation Board Component Side Layout (Not to Scale) Figure 82. Evaluation Board Solder Side Layout (Not to Scale) Rev Page AD9260 ...
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... AD9260 Figure 83. Evaluation Board Ground Plane Layout (Not to Scale) Figure 84. Evaluation Board Power Plane Layout (Not to Scale) Rev Page ...
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... VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range AD9260AS –40°C to +85°C AD9260ASRL –40°C to +85°C 2 AD9260ASZ –40°C to +85°C AD9260ASZRL –40°C to +85°C 2 AD9260- Metric Quad Flatpack Pb-free part. 1.03 0.88 2.45 MAX 0.73 33 SEATING 34 PLANE 7° ...
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... AD9260 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00581–0–7/04(C) Rev Page ...